05-09-2018 02:03 AM - edited 10-15-2019 07:08 AM
This Video Beginner Series 4 shows how to use the Xilinx Video Test Pattern Generator (TPG) in simulation using the Xilinx Verification IP (VIP) to configure it.
The Xilinx Test Pattern Generator (TPG) IP can generate several video test patterns that are commonly used in the video industry for verification and testing.
The selection of the pattern, the size of the output video and many other settings can be configured by configuring the hardware registers using the AXI4-Lite interface of the TPG.
When running on a board, the TPG IP hardware registers are usually programmed using the TPG drivers on a processor like a Microblaze or a Zynq/Zynq MPSoC.
In simulation, you can simplify the design and program the TPG hardware registers using a Verification IP which would act as an AXI4-Lite master.
For information on the Test Pattern Generator, refer to its Product Guide (PG103).
Good to know: The Xilinx TPG is provided at no cost but requires a free license which can be generated from your Xilinx licensing account.
The AXI Verification IP (VIP) can be used to emulate a master/slave interface on three versions of the AXI protocol (AXI3, AXI4, and AXI4-Lite). It can also be used as protocol checker for these three version of the AXI Protocol.
Good to know: To enjoy all the features of the AXI VIP, it must be in a Verilog hierarchy.
Note: This tutorial is intended to be used only with Vivado 2018.1 and only in simulation
Build the Vivado project
Q1. What does this address correspond to?
Q2. From the simulation waveform and the signals on the AXI4-Lite interface, what will be the size of the frame (height and width) outputted by the TPG IP in this case?
Q3. Open the test bench file (tb_tpg.sv) and confirm the settings for the frame size.
Q4. What is the value of the first pixel (m_axis_video_TDATA)?
Q5. What will be the color of the first pixel knowing that the color space is RGB?
Good to know: For a more advance simulation for the TPG, use the example design for this IP. Refer to Chapter 6 of PG103 for information on generating the TPG example design.