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Scholar
Scholar
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Registered: ‎08-07-2014

Video Beginner Series 4 testbench question

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Hello@florentw ,

In the test-bench it is seen that that a wait time of 200ns is inserted before the required bits in the  TPG_CONTROL_REG is set.

Why is this so?

    //Wait for the reset to be released
    wait (aresetn == 1'b1);
    
    #200ns
    //Set TPG output size
    master_agent.AXI4LITE_WRITE_BURST(TPG_ACTIVE_H_REG,0,height,resp);
    master_agent.AXI4LITE_WRITE_BURST(TPG_ACTIVE_W_REG,0,width,resp);
    //Set TPG output background ID
    master_agent.AXI4LITE_WRITE_BURST(TPG_BG_PATTERN_ID_REG,0,9,resp);
    
    #200ns
    // Start the TPG in free-running mode    
    master_agent.AXI4LITE_WRITE_BURST(TPG_CONTROL_REG,0,8'h81,resp);

Why can't we immediately start the axi4lite transaction for the TPG_CONTROL_REG after the TPG_BG_PATTERN_ID_REG is set to value 9?

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Moderator
Moderator
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Registered: ‎11-09-2015

HI @dpaul24 

There is no specific reason. It was just for me to have a nicer waveform to idenfify when I was doing each transaction.

But if you think about it, in a real system, the processor will probably take some time between transactions so to simulate closer to reality it would probably require time between each transaction.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
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Registered: ‎11-09-2015

HI @dpaul24 

There is no specific reason. It was just for me to have a nicer waveform to idenfify when I was doing each transaction.

But if you think about it, in a real system, the processor will probably take some time between transactions so to simulate closer to reality it would probably require time between each transaction.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

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