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fpgause
Observer
Observer
4,143 Views
Registered: ‎11-13-2010

Video Compression in Xilinx video starter kit .........

hi guys.......iam using Accel Dsp of Xilinix  to do compression .i have developed a code for 8 into 8 blocks and also system generator block but then i find that it uses 64 inputs at parallel but i want that only there should be 1 input for serial data flow but i cannot find how i can implement because in script file i have to identify  the arrays for input........

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3 Replies
chrisar
Xilinx Employee
Xilinx Employee
4,098 Views
Registered: ‎08-01-2007

This is probably due to the way you wrote the code.  The number of ports on the block should be based on the number of inputs to the M-Code Function.

You need to serialize the inputs on the M-Code.  Or you will need to use a serial to parallel conversion block in System Generator for DSP.

 

 

Chris
Versal ACAP: AI Engines | Embedded SW Support

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fpgause
Observer
Observer
4,092 Views
Registered: ‎11-13-2010

Can u plz give me any example of script file which takes serial input eg 64 pixels etc becuse i tried alot of methods but can't do it and also no help from the net....... thanks
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shuklaankita
Visitor
Visitor
3,307 Views
Registered: ‎02-22-2013

please can anyone help me about how to interface the lvds camera with ml402 board....

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