cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
722 Views
Registered: ‎12-25-2018

Video Mixer 3.0(Rev 2) failed internal DSP path (Vivado 2018.3)

Jump to solution

Hi,

My setup:

1) Zynq Ultrascale+ xczu9eg-ffvc900-1-e (speedgrade 1)

2) Vivado 2018.3

3) Mixer set to 3 x streaming input interface 64bits (RGBA), 2pixel/clock, 3840 x 2160 size, 1 x streaming output interface 48bits (RGB)

4) Streaming interface running at 300Mhz

After implementation, I get the following timing errors shown below. The mixer internal DSP slice path timing failure.

INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.451 | TNS=-441.244 | WHS=0.010 | THS=0.000 |
INFO: [Physopt 32-952] Improved path group WNS = -0.434. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_2/inst/v_mix_core_alpha123_U0/v_mix_ama_submulacud_U305/design_1_v_mix_2_0_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.405. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_2/inst/v_mix_core_alpha129_U0/v_mix_ama_submulacud_U437/design_1_v_mix_2_0_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.401. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_2/inst/v_mix_core_alpha123_U0/v_mix_ama_submulacud_U305/design_1_v_mix_2_0_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.393. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_2/inst/v_mix_core_alpha123_U0/v_mix_ama_submulacud_U303/design_1_v_mix_2_0_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.388. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_3/inst/v_mix_core_alpha_U0/v_mix_ama_submulacud_U177/design_1_v_mix_1_1_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.373. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_2/inst/v_mix_core_alpha129_U0/v_mix_ama_submulacud_U437/design_1_v_mix_2_0_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.348. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_2/inst/v_mix_core_alpha129_U0/v_mix_ama_submulacud_U436/design_1_v_mix_2_0_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.344. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_3/inst/v_mix_core_alpha_U0/v_mix_ama_submulacud_U177/design_1_v_mix_1_1_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.334. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_2/inst/v_mix_core_alpha123_U0/v_mix_ama_submulacud_U304/design_1_v_mix_2_0_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.324. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_2/inst/v_mix_core_alpha123_U0/v_mix_ama_submulacud_U305/design_1_v_mix_2_0_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.317. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_1/inst/v_mix_core_alpha123_U0/v_mix_ama_submulacud_U307/design_1_v_mix_2_0_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.317. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_2/inst/v_mix_core_alpha129_U0/v_mix_ama_submulacud_U436/design_1_v_mix_2_0_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.310. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_2/inst/v_mix_core_alpha129_U0/v_mix_ama_submulacud_U437/design_1_v_mix_2_0_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.310. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_0/inst/v_mix_core_alpha129_U0/v_mix_ama_submulacud_U434/design_1_v_mix_2_0_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.309. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_0/inst/v_mix_core_alpha129_U0/v_mix_ama_submulacud_U434/design_1_v_mix_2_0_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.293. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_3/inst/v_mix_core_alpha_U0/v_mix_ama_submulacud_U174/design_1_v_mix_1_1_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.286. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_2/inst/v_mix_core_alpha123_U0/v_mix_ama_submulacud_U304/design_1_v_mix_2_0_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.277. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_0/inst/v_mix_core_alpha123_U0/v_mix_ama_submulacud_U304/design_1_v_mix_2_0_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.274. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_3/inst/v_mix_core_alpha_U0/v_mix_ama_submulacud_U177/design_1_v_mix_1_1_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.274. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_3/inst/v_mix_core_alpha_U0/v_mix_ama_submulacud_U175/design_1_v_mix_1_1_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.270. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_2/inst/v_mix_core_alpha123_U0/v_mix_ama_submulacud_U303/design_1_v_mix_2_0_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.269. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_1/inst/v_mix_core_alpha129_U0/v_mix_ama_submulacud_U436/design_1_v_mix_2_0_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.268. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_1/inst/v_mix_core_alpha123_U0/v_mix_ama_submulacud_U307/design_1_v_mix_2_0_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.256. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_2/inst/v_mix_core_alpha129_U0/v_mix_ama_submulacud_U435/design_1_v_mix_2_0_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.253. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_2/inst/v_mix_core_alpha123_U0/v_mix_ama_submulacud_U308/design_1_v_mix_2_0_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.252. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_3/inst/v_mix_core_alpha_U0/v_mix_ama_submulacud_U174/design_1_v_mix_1_1_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.246. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_1/inst/v_mix_core_alpha129_U0/v_mix_ama_submulacud_U433/design_1_v_mix_2_0_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.243. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_2/inst/v_mix_core_alpha129_U0/v_mix_ama_submulacud_U436/design_1_v_mix_2_0_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.242. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_2/inst/v_mix_core_alpha129_U0/v_mix_ama_submulacud_U433/design_1_v_mix_2_0_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.237. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_1/inst/v_mix_core_alpha129_U0/v_mix_ama_submulacud_U432/design_1_v_mix_2_0_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.233. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_2/inst/v_mix_core_alpha123_U0/v_mix_ama_submulacud_U305/design_1_v_mix_2_0_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.228. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_0/inst/v_mix_core_alpha123_U0/v_mix_ama_submulacud_U304/design_1_v_mix_2_0_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.228. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_3/inst/v_mix_core_alpha_U0/v_mix_ama_submulacud_U175/design_1_v_mix_1_1_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.227. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_2/inst/v_mix_core_alpha123_U0/v_mix_ama_submulacud_U306/design_1_v_mix_2_0_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.225. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_0/inst/v_mix_core_alpha129_U0/v_mix_ama_submulacud_U434/design_1_v_mix_2_0_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.224. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_0/inst/v_mix_core_alpha129_U0/v_mix_ama_submulacud_U437/design_1_v_mix_2_0_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.222. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_1/inst/v_mix_core_alpha123_U0/v_mix_ama_submulacud_U305/design_1_v_mix_2_0_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.221. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_2/inst/v_mix_core_alpha123_U0/v_mix_ama_submulacud_U304/design_1_v_mix_2_0_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.216. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_2/inst/v_mix_core_alpha129_U0/v_mix_ama_submulacud_U437/design_1_v_mix_2_0_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.216. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_0/inst/v_mix_core_alpha123_U0/v_mix_ama_submulacud_U307/design_1_v_mix_2_0_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.207. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_1/inst/v_mix_core_alpha129_U0/v_mix_ama_submulacud_U436/design_1_v_mix_2_0_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.203. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_3/inst/v_mix_core_alpha_U0/v_mix_ama_submulacud_U176/design_1_v_mix_1_1_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.197. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_2/inst/v_mix_core_alpha123_U0/v_mix_ama_submulacud_U308/design_1_v_mix_2_0_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.196. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_1/inst/v_mix_core_alpha123_U0/v_mix_ama_submulacud_U303/design_1_v_mix_2_0_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.194. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_1/inst/v_mix_core_alpha129_U0/v_mix_ama_submulacud_U433/design_1_v_mix_2_0_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.193. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_0/inst/v_mix_core_alpha129_U0/v_mix_ama_submulacud_U435/design_1_v_mix_2_0_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.191. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_0/inst/v_mix_core_alpha123_U0/v_mix_ama_submulacud_U305/design_1_v_mix_2_0_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.188. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_1/inst/v_mix_core_alpha123_U0/v_mix_ama_submulacud_U308/design_1_v_mix_2_0_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.187. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_1/inst/v_mix_core_alpha129_U0/v_mix_ama_submulacud_U437/design_1_v_mix_2_0_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.187. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_0/inst/v_mix_core_alpha123_U0/v_mix_ama_submulacud_U308/design_1_v_mix_2_0_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.187. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_0/inst/v_mix_core_alpha129_U0/v_mix_ama_submulacud_U433/design_1_v_mix_2_0_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-952] Improved path group WNS = -0.187. Path group: clk_out1_design_1_clk_wiz_1_0. Processed net: i_design_1/design_1_i/v_mix_1/inst/v_mix_core_alpha129_U0/v_mix_ama_submulacud_U432/design_1_v_mix_2_0_v_mix_ama_submulacud_DSP48_1_U/p/XOROUT[0].
INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.187 | TNS=-246.761 | WHS=0.002 | THS=0.000 |

 

I run the bitstream on the hardware and call the baremetal Mixer driver, the Mixer is able to output video on the monitor at 3840 x2160 resolution. Everything is working even though I got timing error for Mixer internal DSP path.

The I re-run the same project on Zynq Ultrascale+ xczu9eg-ffvc900-2-i (speedgrade 2), the Mixer internal DSP timing failure goes away with WNS = +0.101.

Is there any way to turn on the HLS generated Mixer IP DSP slice pipeline registers for input and output path in order to solve the timing failure? Our project will be using xczu9eg-ffvc900-1-e (speedgrade 1) hardware.

Thanks

 

Regards

AYE

Tags (1)
0 Kudos
1 Solution

Accepted Solutions
watari
Teacher
Teacher
569 Views
Registered: ‎06-16-2013

Hi yan-eng.ang@leica-microsystems.com 

 

Would you refer AR #66314, if the route cause is high fanout or congestion ?

 

https://www.xilinx.com/support/answers/66314.html

 

Best regards,

View solution in original post

0 Kudos
6 Replies
watari
Teacher
Teacher
703 Views
Registered: ‎06-16-2013

Hi yan-eng.ang@leica-microsystems.com 

 

Would you make sure bottleneck in your report file ?

I guess there is too long clock propagation or high fanout issue for data path.

If the former, I suggest you to concern the location of clock source or this block and describe constrains on ex. XDC or optimize option.

If the latter, I sugges you to duplicate the high fanout signal.

 

Best regards,

0 Kudos
florentw
Moderator
Moderator
639 Views
Registered: ‎11-09-2015

HI yan-eng.ang@leica-microsystems.com 

No, I do not believe there is any way to turn on the HLS generated Mixer IP DSP slice pipeline registers for input and output path.

Did you consider moving to 4ppc to reduce the operating frequency?

As per the PG243, the Video mixer should be able to run at 300Mhz on US+ speedgrade 1. However this is check only if the video mixer is alone in the design. This is more complicated when you have more congestion in the design. You might need to dig into your implemented design if you want to have it meeting timing with 2ppc.

Did you also try with different implementation strategies?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
602 Views
Registered: ‎12-25-2018

Hi Florent and Watari,

Thanks for your reply.

I got at least 4 Mixer in the design. To move to 4ppc, it can be quite messy. Maybe can cause difficulty in routing. Right now the whole design is based on 2ppc.

I have try different implementation strategies based timing performance, but it still fails on Mixer DSP path. It is quite consistent.

I did look into the implemented design, all the failure occurs on two DSP slice side by side. I think the only way is to turn on the DSP pipeline registers.

I even try to provide a dedicated 300MHz clock just for the 4 x Mixers in the design, but no luck.

I am not sure whether can move to Zynq Ultrascale+ xczu9eg-ffvc900-2-i (speedgrade 2), but the price will increase alot.

Is there a way to get the HLS Mixer source code, so that I can try to turn on the pipeline registers?

 

 

Regards

YE    

 

0 Kudos
florentw
Moderator
Moderator
584 Views
Registered: ‎11-09-2015

HI yan-eng.ang@leica-microsystems.com 

No the source code for the video mixer is not provided


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
watari
Teacher
Teacher
570 Views
Registered: ‎06-16-2013

Hi yan-eng.ang@leica-microsystems.com 

 

Would you refer AR #66314, if the route cause is high fanout or congestion ?

 

https://www.xilinx.com/support/answers/66314.html

 

Best regards,

View solution in original post

0 Kudos
aoifem
Moderator
Moderator
526 Views
Registered: ‎11-21-2018

Hi yan-eng.ang@leica-microsystems.com 

If your question is answered or your issue is solved, please kindly mark the response which helped as a solution (click on "Accept as solution" button below the reply).

 

If this is not solved/answered, please reply in the topic giving more information on your current status.

 

Thanks and Regards,

 

Aoife
Product Application Engineer - Xilinx Technical Support EMEA


**~ Got a minute? Answer our Vitis HLS survey here! ~**

**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos