simple question really.
Can the Xilinx OSD block Alpha Blend more than 2 input layers?
I have a design, where I feed 3 Xilinx TPG's into an OSD block. I can enable any 2 layers at once and the output is alpha blended, but if I enable the 3rd layer then the OSD stop's outputting data.
many thanks in advance.
As mentioned on the product page of On Screen Display IP, this IP is obsoleted and not supported by Xilinx anymore.