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mehdi_ab
Observer
Observer
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Registered: ‎07-18-2019

Video Out Core timing mode: why not slave with frame buffer

Hi everyone,

pg044 describes 2 timing modes for Video Out core and VTC:

- slave: VTC timing signals are enslaved to pixel flow

-master: VTC free runs and pixel flow is enslaved to VTC timing signals

It is said: " The presence or absence of the VDMA determines how the Video Out core synchronizes timing between the AXI4-Stream data and the VTC, and the timing mode in which the VTC operates" and further, when design involves a Frame Buffer and hence a VDMA IP, master mode should be selected. I do not understand why slave mode cannot be used when pixel come from a frame buffer. Any hint on this would be very helpful.

Thanks in advance,

Mehdi

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rappysaha
Adventurer
Adventurer
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Registered: ‎09-21-2016

Hello mehedi_ab, 

I don't know what is your design exactly. I am guessing 

- first you have tried vdma ip core probably enabling both read and write options. If both options are enabled and if you want to input video timing then slave mode for video out ip should be okay.

- later you may want to add frame buffer ip (read ip guess), read ip usually dont know what is the input timing in that case you need to have video out core in master mode using VTC core. 

Thank you.

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mehdi_ab
Observer
Observer
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Registered: ‎07-18-2019

Hi rappysaha,

thank you for your answer. I did not give any detail of my design because my question was not precisely related to it but  more from a conceptual point of view. I think I will use frame buffe read and write cores as we are implementing a linux based application. So your guess is completely appropriate.  So in slave mode, VTC provides timing signals to video out core when the later needs them. Which means that, in the case of pixel coming from a frame buffer, video out should stall pixel flow during blanking generation and frame buffer read does not need timing information. Maybe it is possible but the solution would be sub-optimal?

With appreciation

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florentw
Moderator
Moderator
181 Views
Registered: ‎11-09-2015

Hi @mehdi_ab 

I do not think this is really a hard rule but most of a guidance.

If you have a frame buffer then you know that you have enough data to keep up with the video timing (and you can repeat frames if needed). So it seems better to use the master mode because you do not want to break the output stream. But I do not think using the slave mode will have a big impact.

While if you do not have a frame buffer then your input data becomes your limitation. So in this case the slave mode becomes more appropriate because you do not want to send only partial data just to keep up with the video timing.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
mehdi_ab
Observer
Observer
153 Views
Registered: ‎07-18-2019

Hi Florent,

Thank you for your answer. This is interesting because I was puzzled by hdmi_tx_ss core with axi4 stream interface: according to figure2-2 in pg235, video out core is in slave mode as its vtg_ce output is connected to clk_en VTC input. And in zcu 106-vcu-trd, this core is used with a frame buffer. So this would be in line with your explanation.

With appreciation

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