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Contributor
Contributor
621 Views
Registered: ‎12-23-2019

Video PHY Controller Clock Resource

Hi,

Video Phy Controller use BUFG by default but I want to change this. According to pg230 documents of Video PHY Controller suggest three tcl command.

How can I implement this command?

set_property -dict [list CONFIG.C_Use_Oddr_for_Tmds_Clkout {false}]
[get_ips <ip name>]
set_property -dict [list CONFIG.C_Tx_Outclk_Buffer {none}] [get_ips <ip
name>]
set_property -dict [list CONFIG.C_Rx_Video_Clk_Buffer {bufg}] [get_ips <ip
name>]

Thanks for reply.

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Xilinx Employee
Xilinx Employee
538 Views
Registered: ‎03-30-2016

Hello @mustafa_d 

Let me try to reproduce your report.
Please wait a moment.

Regards
Leo

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Xilinx Employee
Xilinx Employee
527 Views
Registered: ‎03-30-2016

Hello @mustafa_d 

I just generated DisplayPort TX Example Design, synthesis this, and try to apply the following command.
Result:
Cannot_reproduce_VidPhy_constraint_issue.png

I do not see any errors when applying those "set_property" command.
I also attached my project ( I am using Vivado 2019.2) in this post for your reference. ( Just in case , you want to confirm using my project )

Regards
Leo

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Contributor
Contributor
507 Views
Registered: ‎12-23-2019

Hi @karnanl ,

We use example project for zc706 board and change FPGA with xc7z100iffg-2.

I entered the command as following

set_property -dict [list CONFIG.C_Rx_Video_Clk_Buffer {bufh}] [get_ips <ip name>].

set_property -dict [list CONFIG.C_Tx_Video_Clk_Buffer {bufh}] [get_ips <ip name>]

set_property -dict [list CONFIG.C_Rx_Tmds_Clk_Buffer {bufh}] [get_ips <ip name>]

set_property -dict [list CONFIG.C_Tx_Outclk_Buffer {bufh}] [get_ips <ip name>]

set_property -dict [list CONFIG.C_Tx_Refclk_Fabric_Buffer {bufh}] [get_ips <ip name>]

set_property -dict [list CONFIG.C_Rx_Outclk_Buffer {bufh}] [get_ips <ip name>]

Change bufg usage but this time I get an error for clocking rule.

Which clocking type I choose and I do not get an error (except bufg)?

Thanks for help.

 

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Xilinx Employee
Xilinx Employee
492 Views
Registered: ‎03-30-2016

Hello @mustafa_d 

Yes, I understand that Video PHY use a lot of BUFGs.
You may be able to changes BUFG usage to BUFH using "set_property" ,but you need to understand how the clock is connected in your design.

For example, since BUFH is a horizontal clock buffers, only FF on the same HROW region can be feed.
You will need to ensure that your design is not spread more than a single HROW region, or else BUFG usage is needed, so Vivado will force to cascade BUFG/BUFH.

If you get an error during Vivado implementation, this is most likely that BUFH is connected to FF outside HROW region.
Perhaps PBLOCK setting can help to prevent this error.

Regards
Leo

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Contributor
Contributor
486 Views
Registered: ‎12-23-2019

Hi @karnanl ,

I used PBlock a select all necessary part but I get same error all the time.

Thanks for help

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Xilinx Employee
Xilinx Employee
417 Views
Registered: ‎03-30-2016

Hello @mustafa_d 

Could you please share the error message you got during implementation ?

If you want to reduce VPHY BUFG usage (swap BUFG to BUFH), you need to ensure that BUFH output is not connected to component outside the HROW region.

Regards
Leo

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Contributor
Contributor
393 Views
Registered: ‎12-23-2019

Hi @karnanl ,

Our error as floowing images, I assigned PBlock for other errors but 3 errors left. I can not fix this error because previous I assigned related cell another location because of other errors. I shared our contrait and error.

Thanks for helpIMG_1522.JPGIMG_1523.JPGIMG_1524.JPGIMG_1525.JPGIMG_1526.JPG

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Xilinx Employee
Xilinx Employee
382 Views
Registered: ‎03-30-2016

Hello @mustafa_d 

Thank you for sharing your implementation result.
It is good to hear that implementation errors decreased.

Mustafa_error_message.png

I can see that your BUFH is trying to drive PLL (TXPLL_INST) which is placed in outside the HROW region. This will not work.
Is it possible to swap this BUFH with BUFMR (only for this BUFH) ?
If this is not working, I think you need to use BUFG for this clock buffer.

Regards
Leo

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Contributor
Contributor
375 Views
Registered: ‎12-23-2019

Hi @karnanl 

I changed my design, for this purpose I relocated one pin and rearraged Pblock, now all clock rule status showing pass but I still an error. By the way I tried to BUFMR or BUFR or none but I still get error.

How can detect real error?

Thanks for help.

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Xilinx Employee
Xilinx Employee
364 Views
Registered: ‎03-30-2016

Hello @mustafa_d 

Could you please share the last error message ?

Thank you
Leo

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Contributor
Contributor
355 Views
Registered: ‎12-23-2019

Hi @karnanl ,

Error message same as previous images only change FAIL turn to PASS. All clocking rules seeing PASS.

Thanks for help

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