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Registered: ‎03-07-2018

Video Phy Controller Error

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Hello,

I am getting a place_design_error for my design in VIVADO 2019.1

Error:

[DRC REQP-1927] IBUFDS_GTE4_connects_I_active: IBUFDS_GTE4 design_1_i/vid_phy_controller_0/inst/gt_usrclk_source_inst/IBUFDS_GTE4_MGTREFCLK0_INST pin I has an invalid driver design_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG. Only a direct connection to a Port may drive the IBUFDS_GTE4 pin.

How to solve the error? Please let me know.

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florentw
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379 Views
Registered: ‎11-09-2015

HI sambare.swati@gmail.com 

I do not think the post mentioned by @ashokkum will help here.

The issue is that you are not connecting the Video PHY properly. You try to connect the MGTREFCLK of the Video PHY to the PL clock of the ZynqMP. This is incorrect. As per the error message, you need to connect the NGTREFCLK to an GT clock which is direcly a pin of your FPGA


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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ashokkum
Moderator
Moderator
408 Views
Registered: ‎04-09-2019

Hello sambare.swati@gmail.com ,

This was a known issue and it was already addressed in the forums. Could You please refer the attached link below.

https://forums.xilinx.com/t5/Design-Methodologies-and/Partial-Reconfiguration-need-select-IOB-insertion-to-avoid-DRC/td-p/980020

I hope it helps to You.

With Regards,

Ashok

florentw
Moderator
Moderator
380 Views
Registered: ‎11-09-2015

HI sambare.swati@gmail.com 

I do not think the post mentioned by @ashokkum will help here.

The issue is that you are not connecting the Video PHY properly. You try to connect the MGTREFCLK of the Video PHY to the PL clock of the ZynqMP. This is incorrect. As per the error message, you need to connect the NGTREFCLK to an GT clock which is direcly a pin of your FPGA


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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