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vulinux
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Registered: ‎03-19-2021

Video Processing Subsystem Block Design - Port width mismatch

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Hello,

 

I am using Vivado 2019.1 and targeting a Kintex-7 FPGA (XC7K160T-2FFG676I). The goal of my project is to take YCbCr 4:2:2 format video and convert it to YCbCr 4:4:4 and then into RGB. I am trying to do this by using MicroBlaze processor with the following IP cores:

1) Video In to AXI4-Stream

2) Video Processing Subsystem (Used in YCbCr 4:2:2-4:4:4 Resampling Only mode)

3) Video Timing Controller

4) AXI4-Stream to Video Out.

The idea is to resample the YCbCr 4:2:2 into YCbCr 4:4:4 using these IP cores and then convert the YCbCr 4:4:4 into RGB using a module outside of the block design, which I wrote myself.

 

The problem is that I don't know if I have connected the block design correctly. My main concern is the connection between Video In to AXI4-Stream output port and Video Processing Subsystem input port for video data have different port widths. 

Video In to AXI4-Stream output port has a width of 16 bits and Video Processing Subsystem input port has a width of 24 bits.

There was a critical warning when I validated the desingn but the validation was succesfull in the end. Is this going to be a problem later on? Does Vivado automatically connect the 16b port to the first 16 bits of 24b port? And also I don't know if I need a Interrupt controller. I think I don't but I wanted to check. Does anybody think I will need and Interrupt controller for these IP cores? 

I have attached a photo of the block design and a .7zip of my project (just in case). I would really appreciate any suggestions. Thank you!

block_design.png
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reaiken
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Registered: ‎07-18-2011

@vulinux 

You should add an AXI4-Stream Subset Converter IP block between your Video In to AXI4-Stream IP and your Video Processing Subsystem IP block.

Double-click on the Subset Converter and manually set the Tdata width for the Slave interface to 2 bytes and the Tdata width for the Master interface to 3 bytes.

You don't need the interrupt controller for your design.

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reaiken
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Registered: ‎07-18-2011

@vulinux 

You should add an AXI4-Stream Subset Converter IP block between your Video In to AXI4-Stream IP and your Video Processing Subsystem IP block.

Double-click on the Subset Converter and manually set the Tdata width for the Slave interface to 2 bytes and the Tdata width for the Master interface to 3 bytes.

You don't need the interrupt controller for your design.

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Nikhil_Thapa
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Registered: ‎05-28-2020

Hi @vulinux ,

Video In to AXI4-Stream output port has a width of 16 bits and Video Processing Subsystem input port has a width of 24 bits.

You have to check these parameters of video In to Axi4-stream.

Nikhil_Thapa_0-1620368279963.png

 

The port width is changed according to above parameters. Would you check those again? Generally, changing the video format changes the width.

 

Is this going to be a problem later on?

No, unless your incoming AXI4-Stream is correct.

 

Does Vivado automatically connect the 16b port to the first 16 bits of 24b port?

Yes, but only the LSB bits are connected. Other higher bits will be tied to zeros. You can let this as it is or you can use Subset Converter IP as @reaiken says.

 

Does anybody think I will need and Interrupt controller for these IP cores?

No, you will not need at this moment. Video In to AXI4-Stream IP does not have Interrupt Pin but Video Processing Subsystem IP has. Interrupt thing is not related with stream width but the entire operation of IP.

 

Thanks and Regards,

nikhil@logictronix.com
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vulinux
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Registered: ‎03-19-2021

Hello @Nikhil_Thapa,

Thanks for the quick reply. I have checked the Video In to AXI4-Stream settings again and I added a picture.

 

I chose the format to be YUV 4:2:2 because that's the format my design is receiving (8 bits for the Y channel and 8 bits for the Cb/Cr channel because Chroma is subsampled). I am gessing that is why the output of Video In to AXI4-Stream is 16b wide.

videoin_setup.png
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