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venugopal.kulkarni
Contributor
Contributor
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Registered: ‎11-06-2019

Video Processing Subsystem Clock Frequency (Auto)

Hi.

I am stuck with an Issue.

I have an existing design for Video Data. where I want to convert the RGB data into YUV. For this conversion I wanted to use Video Processing Subsystem IP.

The issue is whenever I am making connection, Between AXI_DMA and VPSS It's showing error "Bus Interface property Freq_HZ does not match".

Even If I am connecting the same clock for both the Blocks: VPSS and AXI_DMA. The individual interface of both blocks show different frequency in their properties. The AXI-DMA side shows 266.5 MHz and the VPSS side shows 100 MHz.

 

I have also attached the screenshots for the reference. Waiting for your Valuable Reply.

Block_Diamgram_1.JPG
AXI-stream_AXI-DMA.JPG
AXI-stream_vpss.JPG
Error_message.JPG
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8 Replies
watari
Professor
Professor
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Registered: ‎06-16-2013

Hi @venugopal.kulkarni 

 

Because there are some open ports on VPSS, you are facing this issue.

Would you connect proper signals ?

 

Best regards,

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Nikhil_Thapa
Explorer
Explorer
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Registered: ‎05-28-2020

Hi @venugopal.kulkarni ,

It's showing error "Bus Interface property Freq_HZ does not match".

Absolutely, frequency is not matched. You are feeding clock to "aclk_axi_mm" pin of VPSS only. This pin is used for memory mapped clocking, not for AXI4-Stream clock. You need to connect same clock to "aclk_axis"  of VPSS that you are connecting to "m_axi__mm2s_aclk" of AXI DMA IP. 

Nikhil_Thapa_0-1622466222027.png

 

 

 

Regards,

nikhil@logictronix.com
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venugopal.kulkarni
Contributor
Contributor
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Registered: ‎11-06-2019

I have the same issue Even if I connect those ports. My main concern is, it shows different Frequencies in clock properties of the same line at two blocks. I have connected the same clock.

Please refer another block diagram where i have connected the ports.

Please guide me.

Block_Diamgram_2.JPG
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Nikhil_Thapa
Explorer
Explorer
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Registered: ‎05-28-2020

@venugopal.kulkarni , your block design is not very clear. 

aclk of VPSS and m_axi_mm2s_aclk of AXI DMA must have same clock domain. Can you check again? or you can share your BD here.

Is your problem really related to AXI DMA and VPSS?

Nikhil_Thapa_0-1622476389012.png

But your error messages say that frequency is not matched between RGB2YCbCr and AXI DMA IP block. Would you check it once more?

 

Regards,

nikhil@logictronix.com
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venugopal.kulkarni
Contributor
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Registered: ‎11-06-2019

Now after connecting as suggested. Now its not showing the CLK error but now i am stuck at a point.

In data sheet it says " Control of the video processing pipe is only supported through the Video Processing
Subsystem driver".

Which signals shall I provide to this s_axi_ctrl port of VPSS?

Please provide the details. refer the block diagram for your reference.

My main aim is to convert the data in YUV format.

VPSS_Block_Diamgram.JPG
Error_message_AXI_ctrl.JPG
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Nikhil_Thapa
Explorer
Explorer
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Registered: ‎05-28-2020

Hi @venugopal.kulkarni , 

Which signals shall I provide to this s_axi_ctrl port of VPSS?

This s_axi_ctrl port is the AXI-Lite interface of the VPSS, by which VPSS is configured from software side. This is the Slave Interface, which you need to connect it to Master Interface of Zynq Processing System through AXI Interconnect.

Nikhil_Thapa_0-1622621623778.png

 

From your BD, you have already connected s_axi_ctrl to the AXI Interconnect. Now, you need to connect S00_AXI port of AXI Interconnect to Master Interface of the Zynq Processing System. And you also have to connect correct clock signal and reset signal for S00_AXI and M00_AXI. Otherwise, you will again get Clock frequency issue, like you were getting previously.

 

Regards,

nikhil@logictronix.com
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venugopal.kulkarni
Contributor
Contributor
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Registered: ‎11-06-2019

Now whenever i am trying to make connection its not able to connect.

S00_AXI port of AXI Interconnect and s_axi_ctrl of VPSS both are not getting connected to ZYNQ processor block. It says no matching port available in Block design.

I tried removing and reinserting the ZYNQ Processing Block but it shows same for the new block.

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Nikhil_Thapa
Explorer
Explorer
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Registered: ‎05-28-2020

@venugopal.kulkarni ,

S00_AXI port of AXI Interconnect and s_axi_ctrl of VPSS both are not getting connected to ZYNQ processor block. It says no matching port available in Block design.

Well, what are you doing? Are you trying to connect s_axi_ctrl to Zynq PS block directly? No, you cannot connect it. You need AXI Interconnect IP. However, you have already used AXI Interconnect IP. You can simply connect S00_AXI port to the M_AXI_GP port of Zynq PS block.

 

Regards,

nikhil@logictronix.com
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