cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Observer
Observer
513 Views
Registered: ‎05-28-2020

Video Processing Subsystem is not giving output

Jump to solution

Hello Everyone,

I am working on implementation of Full Fledged Video Processing Subsystem project on PYNQ-Z1 board.
I am following Xilinx video series tutorial on VPSS. And I have also used the vprocss example code in SDK.
Unlike the tutorial, I am feeding video stream from HDMI source rather than TPG to vprocss IP. Everything is going good but
not getting any output so far.
I have attached a part of block design, debug report and ILA status below.

From the debug report, it seems that vprocss is well configured. However, from its ILA status, data is not streaming out because, TREADY and TVALID are always in LOW states.
Why am I not getting any output? What are things that I must consider and take care for the design with Video Processing Subsystem IP?
Thank you.

vprocss_bd.png
vprocss waveform.png
0 Kudos
1 Solution

Accepted Solutions
Highlighted
Observer
Observer
255 Views
Registered: ‎05-28-2020

Sorry for the delay. And thank you for suggesting the video series.
Well, I have done both of series in a single VPSS IP.
Initially, I did scalar only mode. Later on, I enabled CSC. I did as exactly as you said. But it was not working so far. The monitor was showing "OUT OF RANGE". Later, I found that the problem was due to the pixel clock generated by Clocking Wizard IP.
And I also checked the SDK code, where I found that the hex value, which was used to generate pixel clock for particular video mode, was not working on my board. Because, input frequency that I supplied to clocking wizard, was different than ZC702.

According to following section from PG065 
2020-07-16 15_15_19-Clocking Wizard v6.0 LogiCORE IP Product Guide.png2020-07-16 15_16_15-Clocking Wizard v6.0 LogiCORE IP Product Guide.png

 

 

 

 

 

 

 

I did re-calculation of all the pixel clock frequencies, based on the input clock frequency that I supplied to clocking wizard. After that VPSS, in scalar mode, worked flawlessly.
And the other thing is, while doing color space conversion, initially, I did not get RGB video format at the output. Later, I found that the video series was made to support 16 bit color format for ZC702 board. So, I did modification in both hardware and software to support 24 bit color format. And then, it worked as expected.
Then after, I did Full-Fledged mode. There, I designed both hardware and software taking care all of the things from Video Series 27 , Video Series 28 , Video Series 29 and Video Series 30 .
Now, VPSS full-fledged mode in PYNQ-Z1 works perfectly.

Thanks again @florentw .

View solution in original post

8 Replies
Highlighted
Moderator
Moderator
493 Views
Registered: ‎11-09-2015

Hi @Nikhil_Thapa 

What about the state of the signals coming from the others IPs?

According to the AXI4 Specification, a slave can wait for a master to assert tvalid before asserting tready. So when you are capturing the signals with an ILA, I suggest you include all the signals.

I might really be that you have no data coming in, so it is expected that no data will be coming out

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Highlighted
Observer
Observer
467 Views
Registered: ‎05-28-2020

Thank you for reply and suggestion.
Here, I have attached the signals state for both incoming and outgoing signals to and from VPSS IP.
Here, I see both the signals, TVALID and TREADY of incoming stream, are in HIGH states. Therefore, VPSS IP is receiving input data.

But, VPSS IP is not asserting TVALID signal at the output.

input and output signals state.png
0 Kudos
Highlighted
Moderator
Moderator
456 Views
Registered: ‎11-09-2015

Hi @Nikhil_Thapa 

How long are you waiting?

Can you show the output of the journal from the VPSS late in the flow?

Are you using the same code as in the Video Series?

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Highlighted
Observer
Observer
388 Views
Registered: ‎05-28-2020

@florentw wrote:

Hi @Nikhil_Thapa 

How long are you waiting?

Can you show the output of the journal from the VPSS late in the flow?

Are you using the same code as in the Video Series?

 


How long are you waiting?

I used auto trigger-mode with refresh rate 1024 ms and then I waited 5-10 minutes for ILA status. I got nothing changed in the signal states.

Here, I have attached two ILA waveform below, after doing some sort of sdk code modification.

At first, I did not add any sort of reset code. So, I got the ILA status as shown in Figure (a) waveform. This waveform is same as that of my previous reply waveform

But, in second time, I added vprocss reset code. And then I got different ILA status, as shown in Figure (b). I saw TREADY signal was asserted but TVALID signal always remained at LOW state.

ILA status before adding reset codeILA status before adding reset codeILA status after adding reset codeILA status after adding reset code

Are you using same code as in the video series?

Exactly, I have used same code. Unlike the video series, I am taking video stream from HDMI source rather than TPG. Therefore, I have modified the code little bit by removing TPG related codes. All the initialization and vprocss start codes are exactly same. However, I have only modified the code for setting the vprocss input and output stream parameters.

Here is the modified code I used,

vprocss stream parameters.png

 

 

 

 

 

Can you show that output of the journal from the VPSS late in the flow?

I do not understand what you are exactly saying.

0 Kudos
Highlighted
Moderator
Moderator
378 Views
Registered: ‎11-09-2015

@Nikhil_Thapa wrote:

Can you show that output of the journal from the VPSS late in the flow?

I do not understand what you are exactly saying.


See Advice #4 from Video Series 27: Getting started with the Video Processing Subsystem IP

But run the API after the configuration of the VPSS

What you can try as well is keeping the TPG and use the AXI4-Stream input on it and do path-trough. So you will stay close from the original design


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Highlighted
Observer
Observer
334 Views
Registered: ‎05-28-2020

@florentw wrote:
See Advice #4 from Video Series 27: Getting started with the Video Processing Subsystem IP

I reviewed the entire video series 27 including your Advice #4 with my project. Everything is fine according to this video series. VPSS still does not work.


@florentw wrote:

But run the API after the configuration of the VPSS


I always run the API after the configuration of the VPSS. There is no doubt about it.


@florentw wrote:
What you can try as well is keeping the TPG and use the AXI4-Stream input on it and do path-trough. So you will stay close from the original design

I designed hardware block, where I fed the video stream from TPG to VPSS. I also added two ILAs at the input and output section of VPSS to check the input and output signal states.

I waited for 5-10 minutes for ILA status. I got the signal states. However, in the input section, I found that TPG was asserting TVALID signal but VPSS was never asserting TREADY signal.

ILA status of input sectionILA status of input section

 

 

 

 

 

 

 

In the output section, I found that TREADY signal was asserted by other IP but VPSS was never asserting TVALID signal.

ILA status of output sectionILA status of output section

 

 

 

 

 

 

 

What might be the reason behind this problem? Is this because of bug in the hardware or software?

I have attached the VPSS log information, harware block design and main sdk code below.

 

0 Kudos
Highlighted
Moderator
Moderator
301 Views
Registered: ‎11-09-2015

Hi @Nikhil_Thapa 

Can you try first with exactly the same as the video series, i.e. either using CSC (Video Series 28: Using the VPSS IP in Color Space Converter mode) mode only or Scaler only mode (Video Series 29 – Understanding Video Scaling – Example with VPSS IP)?

 

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Highlighted
Observer
Observer
256 Views
Registered: ‎05-28-2020

Sorry for the delay. And thank you for suggesting the video series.
Well, I have done both of series in a single VPSS IP.
Initially, I did scalar only mode. Later on, I enabled CSC. I did as exactly as you said. But it was not working so far. The monitor was showing "OUT OF RANGE". Later, I found that the problem was due to the pixel clock generated by Clocking Wizard IP.
And I also checked the SDK code, where I found that the hex value, which was used to generate pixel clock for particular video mode, was not working on my board. Because, input frequency that I supplied to clocking wizard, was different than ZC702.

According to following section from PG065 
2020-07-16 15_15_19-Clocking Wizard v6.0 LogiCORE IP Product Guide.png2020-07-16 15_16_15-Clocking Wizard v6.0 LogiCORE IP Product Guide.png

 

 

 

 

 

 

 

I did re-calculation of all the pixel clock frequencies, based on the input clock frequency that I supplied to clocking wizard. After that VPSS, in scalar mode, worked flawlessly.
And the other thing is, while doing color space conversion, initially, I did not get RGB video format at the output. Later, I found that the video series was made to support 16 bit color format for ZC702 board. So, I did modification in both hardware and software to support 24 bit color format. And then, it worked as expected.
Then after, I did Full-Fledged mode. There, I designed both hardware and software taking care all of the things from Video Series 27 , Video Series 28 , Video Series 29 and Video Series 30 .
Now, VPSS full-fledged mode in PYNQ-Z1 works perfectly.

Thanks again @florentw .

View solution in original post