cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
3,383 Views
Registered: ‎01-09-2018

Video Processing Subsystem scaler output - supports all resolutions?

I'm using the VPSS 2.0 in Vivado 2017.3. It's set for 1 sample per clock, maximum data width 8, maximum resolution 1920x1080, full fledged, interlacing disabled, DMA enabled, color space support "RGB | YUV 4:4:4 | YUV 4:2:2", scaler bilinear, chroma resampler FIR and 4 horizontal taps, demo window disabled. Although YUV is enabled, I am using RGB.

 

The input to the VPSS is a 720p camera (1280x720, 60 fps, 74.25 MHz pixel clock) going into a "Video In to AXI4-Stream". The output of the VPSS is going into a Video Mixer 2.0. This setup is working great, but now I am trying to use the scaling feature of the VPSS to change the camera feed to an arbitrary size and display it using the mixer. I'm finding that at certain widths, the scaler output gets completely corrupted. For example, an output width of 105 or 106 pixels works great, but 102, 103, 104, 107, 108, or 109 pixels experiences the corruption.

 

Any ideas about what might be causing this? Does the VPSS not support scaling to any arbitrary resolution? Could I be calculating the stride incorrectly when calling XVMix_SetLayerWindow?

 

Example code after VPSS and mixer have already been set up drawing full 1280x720 video:

 

uint16_t width = 300, height = 300, x = 100, y = 100;

XVMix_LayerDisable(&mix, XVMIX_LAYER_1);
usleep(10000);
XVprocSs_Stop(&vpss[1]); _pipOutputStream.Timing.HActive = width; _pipOutputStream.Timing.VActive = height; _pipOutputStream.ColorFormatId = XVIDC_CSF_RGB; _pipOutputStream.FrameRate = XVIDC_FR_60HZ; _pipOutputStream.IsInterlaced = 0; _pipOutputStream.ColorDepth = static_cast<XVidC_ColorDepth>(XVIDC_BPC_8); _pipOutputStream.PixPerClk = static_cast<XVidC_PixelsPerClock>(XVIDC_PPC_1); XVprocSs_SetVidStreamOut(&vpss[1], &_pipOutputStream); XVprocSs_ResetZoomModeFlag(&vpss[1]); XVprocSs_SetSubsystemConfig(&vpss[1]); usleep(10000);
XVidC_VideoWindow window; XVMix_SetLayerAlpha(&mix, XVMIX_LAYER_1, 256); XVMix_SetLayerScaleFactor(&mix, XVMIX_LAYER_1, XVMIX_SCALE_FACTOR_1X); window.Width = width; window.Height = height; window.StartX = x; window.StartY = y; XVMix_SetLayerWindow(&mix, XVMIX_LAYER_1, &window, width*4); XVMix_LayerEnable(&mix, XVMIX_LAYER_1);

Using the parameters above (width=300, height=300) will exhibit the graphical corruption, but setting width to 400 works fine. Height doesn't seem to matter, but various widths seem to be able to cause problems. The video mixer doesn't seem to have any problems throughout this process. Problematic output width settings are 100% repeatable--it doesn't seem to be random. I would appreciate any input. Thanks!

Tags (2)
0 Kudos
Reply
18 Replies
Highlighted
Moderator
Moderator
3,347 Views
Registered: ‎11-09-2015

Hi @dougskl,

 

Which color spaces are you using as input and output? The main point for me is to know if you are using the color space converter inside the VPSS.

 

If you are using YUV422, could you try to use the chroma ressample IP before the VPSS to convert your input to YUV444?

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Reply
Highlighted
Visitor
Visitor
3,337 Views
Registered: ‎01-09-2018

Hi Florent,

 

Thank you for your reply. I am using YUV422 as input and RGB as output. I just tried what you suggested (inserting a Chroma Resampler for YUV422->YUV444 conversion before the VPSS) and changing the VPSS to use YUV444 as an input. The scaler is still corrupting video at the same widths.

 

Below is a video showing the corruption I'm seeing, using my latest bitstream that uses the Chroma Resampler IP for the 422->444 conversion. Both video inputs are 720p60. When the subwindow is working, the VPSS is configured to scale to 400x300. When it's not working, it's configured to scale to 401x300.

 

 

Any ideas? After this video was taken, I also tried adding a "YCrCb to RGB Color-Space Converter" after the Chroma Resampler and setting the VPSS to be RGB->RGB. The corruption is still present in that configuration, but without the red and green tint.

 

Thanks,

Doug

0 Kudos
Reply
Highlighted
Moderator
Moderator
3,307 Views
Registered: ‎11-09-2015

Hi @dougskl,

 

I was not expecting this as corruption. It looks like the stream is not synchronized.

 

The VPSS can be generated in an example design. Could you try to use the example design application as reference for your application? This is because the VPSS require specific steps when starting or changing resolution (need to stop + reset the stream...)

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Reply
Highlighted
Visitor
Visitor
3,255 Views
Registered: ‎01-09-2018

Hi @florentw,

 

Thanks. Do you mean to use the sample C code from the example design? Although I have a license for the VPSS, I am using the WebPACK and thus do not have a license for the KC705 board that the example design uses, so I have never been able to open the VPSS example in Vivado. I should still be able to test the sample C code though. Is this the example code you are talking about?

 

https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/vprocss/examples/src

 

I will say that this problem still occurs if I change the code to start out at one of the problematic resolutions, so that I'm not changing anything live. I am definitely following the general set of steps that is shown in the code linked above:

 

XVprocSs_LookupConfig()

XVprocSs_SetFrameBufBaseaddr()

XVprocSs_CfgInitialize()

XVprocSs_SetVidStreamIn()

XVprocSs_SetVidStreamOut()

XVprocSs_SetSubsystemConfig()

 

A couple of other things I tried:

 

1) Test pattern generator creating a 401x300 test pattern fed directly into the video mixer works fine.

2) Test pattern generator creating a 1280x720 test pattern, fed into the VPSS configured to scale from 1280x720 to 401x300, fed into the video mixer with identical configuration, has the corruption.

3) Same as #2, but configured for 400x300 instead of 401x300, works fine.

 

Thanks,

Doug

0 Kudos
Reply
Highlighted
Visitor
Visitor
3,268 Views
Registered: ‎01-09-2018

Hi @florentw,

 

Thanks. For some reason my previous reply disappeared after I edited it, so trying again...

 

Do you mean to use the sample C code from the example design? Although I have a license for the VPSS, I am using the WebPACK and thus do not have a license for the KC705 board that the example design uses, so I have never been able to open the VPSS example in Vivado. I should still be able to test the sample C code though. Is this the example code you are talking about?

 

https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/vprocss/examples/src

 

I will say that this problem still occurs if I change the code to start out at one of the problematic resolutions, so that I'm not changing anything live. I am definitely following the general set of steps that is shown in the code linked above:

 

XVprocSs_LookupConfig()

XVprocSs_SetFrameBufBaseaddr()

XVprocSs_CfgInitialize()

XVprocSs_SetVidStreamIn()

XVprocSs_SetVidStreamOut()

XVprocSs_SetSubsystemConfig()

 

A couple of other things I tried:

 

1) Test pattern generator creating a 401x300 test pattern fed directly into the video mixer works fine.

2) Test pattern generator creating a 1280x720 test pattern, fed into the VPSS configured to scale from 1280x720 to 401x300, fed into the video mixer with identical configuration, has the corruption.

3) Same as #2, but configured for 400x300 instead of 401x300, works fine.

 

Thanks,

Doug

0 Kudos
Reply
Highlighted
Moderator
Moderator
3,261 Views
Registered: ‎11-09-2015

Hi @dougskl,

 

Yes this is the example I am talking about.

 

401x300 is a weird resolution. It is not really common to have odd resolution so it might have not been tested.

 

Could you try to do a counter and check if the VPSS is outputting the correct number of pixels for each lines or each frames? You can use the video debug module for this (see AR#59790).

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Highlighted
Visitor
Visitor
3,249 Views
Registered: ‎01-09-2018

Hi @florentw,

 

Thanks for the tip about the video debug module -- I didn't know this existed, and it would have been very useful earlier during the design process! :-)

 

401x300 is definitely a weird resolution, agreed. Since I'm using the video mixer, I can accept any frame size. The ultimate goal is to allow the user to set the size of a picture-in-picture video with a touchscreen interface, and I just happened to notice that some frame sizes worked, and some frame sizes didn't.

 

I tested out the debug module, and the VPSS is indeed outputting valid 401x300 frames. I talked to the video debug module through the AXI4-Lite interface and looked at the frame history FIFO. None of the error bits are getting set, and every frame is 401x300.

 

Frame 0 is 401x300 with err_eol_early=0, err_eol_late=0, err_sof_early=0, err_sof_late=0.
Frame 1 is 401x300 with err_eol_early=0, err_eol_late=0, err_sof_early=0, err_sof_late=0.
.........
Frame 1023 is 401x300 with err_eol_early=0, err_eol_late=0, err_sof_early=0, err_sof_late=0

 

It seems as though the VPSS is outputting valid frames, but they contain incorrect data. I am starting to think there is a bug in the VPSS's horizontal scaler...any thoughts?

 

Thanks,

Doug

0 Kudos
Reply
Highlighted
Moderator
Moderator
3,239 Views
Registered: ‎11-09-2015

Hi @dougskl,

 

Did you try to input 401x300 from a TPG to the video mixer just to check if it is working and the issue is really coming from the VPSS?

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Reply
Highlighted
Visitor
Visitor
3,231 Views
Registered: ‎01-09-2018

Hi @florentw,

 

Yes -- I tried that, and the video mixer displayed the 401x300 test pattern perfectly with no problems. I also tried feeding a 1280x720 test pattern into the VPSS (scaling it to 401x300), and the VPSS corrupted it. That's why I'm pretty sure I have it narrowed down to a problem in the VPSS. There are a lot of horizontal resolutions that don't scale properly.

 

Doug

0 Kudos
Reply
Highlighted
Moderator
Moderator
3,200 Views
Registered: ‎11-09-2015

Hi @dougskl,

 

Are you using a Xilinx development board? If yes could you share your design TPG->VPSS->MIXER->out with me, I can have a look.

 

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Reply
Highlighted
Visitor
Visitor
3,195 Views
Registered: ‎01-09-2018

Hi @florentw,

 

Unfortunately I'm not -- I'm on a custom board at this point. I think we do have a ZedBoard laying around somewhere, but I'm not sure if I will have time to move my design to it for a couple of weeks (do you have access to a ZedBoard?). I could at least share an example of the setup code for the mixer and VPSS.

0 Kudos
Reply
Highlighted
Moderator
Moderator
3,193 Views
Registered: ‎11-09-2015

Hi @dougskl,

 

If you can strip the design to keep only the VPSS, TPG and video Mixer and send me this design (SW+HW) it would be enough (this can be shared in Private). I will take care of moving it to a Xilinx board to try.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Reply
Highlighted
Visitor
Visitor
3,179 Views
Registered: ‎01-09-2018

Hi @florentw,

 

Thank you. I have sent you a private message with a link to download the stripped design. Note that I am using an ADV7511 for HDMI output, so there is a section of code that configures the ADV7511.

 

For anybody else reading along: I have attached an image of the output that the stripped design generates. The background is generated by a 1280x720 test pattern generator. The top-left layer is a 1280x720 test pattern passed through a VPSS configured to scale to 401x300. It is supposed to be color bars, just like the bottom-right layer. But instead it is corrupted. The bottom-right layer is a 401x300 test pattern generator fed directly to the mixer. This shows that the mixer can handle 401x300 without problems and it seems to be the VPSS causing the corruption while scaling.

 

Thanks,
Doug

IMG_7365.jpg
0 Kudos
Reply
Highlighted
Moderator
Moderator
3,107 Views
Registered: ‎11-09-2015

HI @dougskl,

 

Sorry about the delay. I spent some time to rebuild your design and moving it to ZC706.

 

I still have some issues (with the color space) but I can see your issue. I will investigate.

 

Do you have any updates from your side?

 

Thanks,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Reply
Highlighted
Visitor
Visitor
3,097 Views
Registered: ‎01-09-2018

Hi @florentw,

Thank you for rebuilding the design. Your color space issues might be related to differences in board wiring of the color data pins or something. I don’t have any updates on my end—I’m at a trade show right now. I restricted our user interface to only allow a few specific known good resolutions for now to work around the issue, but it would be great if all resolutions worked properly.

Thanks,
Doug
0 Kudos
Reply
Highlighted
Moderator
Moderator
3,091 Views
Registered: ‎11-09-2015

Hi @dougskl,

 

I have fixed my colour space issue. I was configuring the ADV7511 incorrectly.

 

I am changing the configuration of the VPSS to scaler only to see if I still have the issue so if it is coming from the scaler (I avoid any transfer to memory)

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Reply
Highlighted
Teacher
Teacher
3,080 Views
Registered: ‎06-16-2013

Hi @dougskl

 

I guess it seems the route cause is an irregular tlast issue or mismatch of horizontal active size between scaler and VDMA or incorrect horizontal setting on VDMA.

 

Could you show the related register values ?

 

I had a similar issue when I used my ASIC design with scaler and DRAM controller.

 

Best regards,

 

0 Kudos
Reply
Highlighted
Visitor
Visitor
3,063 Views
Registered: ‎01-09-2018

Hi @florentw,

 

Thanks, and glad you figured out the ADV7511 issue. I am excited to hear what you discover.

 

@watari, thank you for the suggestions. As far as I can tell, Xilinx isn't officially publicly documenting the VPSS registers -- it seems to be that we are supposed to use their sample driver code to control it, which is what I have been doing. I'm guessing they are probably pretty similar to the previous separate IP cores for the scaler, chroma resampler, etc., but I don't know for sure.

0 Kudos
Reply