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Registered: ‎11-09-2015

Video Series 19: Using the On-Board HDMI on ZC702 (Vivado design)




This Video Series 19 shows an example of Hardware Design which can output video on the On-Board HDMI output of the ZC702 using the ADV7511.

This design will need a software application to work. This will be done in the following Video Series.






1. On-Board HDMI on ZC702 (ADV7511)

2. Tutorial – Build a HDMI TX design for ZC702

3. What Next?



On-Board HDMI on ZC702 (ADV7511)

ADV7511 on ZC702

The ZC702 on-board HDMI Video Output is documented in UG850 p34 (v1.6.1):

The ZC702 board provides a high-definition multimedia interface (HDMI®) video output using an Analog Devices ADV7511KSTZ-P HDMI transmitter at U40. The HDMI output is provided on a Molex 500254-1927 HDMI type-A receptacle at P1. The ADV7511 supports 1080P 60Hz, YCbCr 4:2:2 encoding via 16-bit input data mapping.

The HDMI codec circuit is shown in the following figure (figure 1-15 from UG850):




What we can see from this figure is that there are only 16 data pins connected to the ADV7511. Thus, it can be used to output 8-bits YCbCr422.

ADV7511 Hardware User’s Guide

The Hardware User’s Guide for the ADV7511 can be found on Analog Website:

In this documentation we can see the different configurations in table 5 to table 16. With the connection on the ZC702 (data connected from D8 to D23), we can see that we can use the format presented in table 7 (with style 1,2 or 3).


Configuration of the ADV7511

The ADV7511 needs to be configured using the I2C interface.

As we can see from the following figure (figure 1-16 from UG850), the ZC702 HDMI codec can be programmed using the I2C from the PS (Processing System) or from the PL (Programmable Logic). In our design we will use the I2C from the PS.



The U44 on the figure above is an I2C switch and its address is 0x74. It must be addressed and configured first to select the desired downstream device. We will see this in a next Video Series.


Tutorial – Build a HDMI TX design for ZC702

Note: This tutorial is intended to be used only with Vivado 2018.1 and only with the ZC702

Build the Vivado project

  1. Download the tutorial files and unzip the folder

  2. Open Vivado 2018.1

  3. In the tcl console, cd into the unzipped directory (cd <path>/XVES_0019)

  4. In the tcl console, source the script tcl (source ./create_proj.tcl)

Note: A valid license for the Test Pattern Generator is required to build the design.

The block design already has an AXI4-Stream to Video Out IP configured for YUV422 and connected to the Block Design (BD) output and a clocking wizard to generate the video clock.

Note that the project includes a constraints file (ZC702.xdc) containing the pin locations for the design outputs. These constraints are taken from the Appendix C of UG850 (with the pin names changed to match the BD outputs).


Add the Zynq Processor

  1. Right-click on the Block Design and click Add IP. Search for Zynq and add the ZYNQ7 Processing System

  2. On the top of the Block Diagram window, click on Run Block Automation



  1.  In the Run Block Automation window, leave the default parameters (make sure apply board preset is checked) and click OK. This will configure the Zynq for the ZC702 board automatically


If we double click on the Zynq IP to open its configuration GUI, we can see that the I2C interface has been enabled (as well as the UART).


Add the Video Pipeline

  1. Add a Video Timing Controller (VTC) IP to the Block design

  2. Double click on the VTC IP to configure it

  3. In the Detection/Generation page, disable Include AXI4-Lite Interface and Enable Detection


  1. In the Default/Constant page select 800x600p for the video mode and click OK


  1. Connect the VTC output vtiming_out to the AXI4-Stream to Video Out IP input vtiming_in and the AXI4-Stream to Video Out IP output vtg_ce to the VCT input gen_clken.


  1. Connect the clk input from the vtc to the clk_out1 output of the Clocking wizard

  2. Add a Test pattern generator to the Block design

We know from the Video Beginner Series 12 that if we want to connect the TPG to the AXI4-Stream to Video Out IP for YUV422 data, we need to use an AXI-Subset converter in-between

  1. Add an AXI4-Stream Subset Converter IP

  2. Double click on the AXI4-Stream Subset Converter IP to open its configuration GUI and set tdata width to 3 for the slave interface and 2 for the master interface



  1. Connect the AXI4-Stream interfaces of the TPG, AXI4-Stream Subset Converter and AXI4-Stream to Video out




  1. Click on Run Connection Automation



  1. Enable All Automations and click OK




This step will automatically connect the AXI4-Lite interface from the TPG to the Zynq processor and the clocks and resets to the AXI4-Stream Subset converter and the AXI4-Stream to Video Out.


  1. Validate the BD, there should be no error. Save the BD.

  2. In the Sources Window, right-click on the BD ( and click Generate Output Products.



  1.  Click Generate on the Generate Output Products pop up window


  1. When the Output Products Generation is over, right-click again on the BD ( and click Create HDL Wrapper…




  1. Select Let Vivado manage wrapper and auto-update



  1. In the flow navigator, click on Generate Bitstream

  2. Click yes on the next pop up window. The tool only warn that it will need to run synthesis and implementation before generating the bitstream


  1.  Once the bitstream is generated, export the Hardware Definition File (hdf) to be used in SDK by clicking on File > Export > Export Hardware…



  1.  In the Export Hardware pop up window, enable Include bitstream and click Ok

This will create a .sdk directory with the hdf file inside. We will use this hdf file in the next Video Series




29.  Close Vivado

What Next?


  • Do you have issues/questions following this Vivado Beginner Series?
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Product Application Engineer - Xilinx Technical Support EMEA
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