11-28-2018 05:20 AM - edited 11-28-2018 05:41 AM
This Video Series 19 shows an example of Hardware Design which can output video on the On-Board HDMI output of the ZC702 using the ADV7511.
This design will need a software application to work. This will be done in the following Video Series.
The ZC702 on-board HDMI Video Output is documented in UG850 p34 (v1.6.1):
“The ZC702 board provides a high-definition multimedia interface (HDMI®) video output using an Analog Devices ADV7511KSTZ-P HDMI transmitter at U40. The HDMI output is provided on a Molex 500254-1927 HDMI type-A receptacle at P1. The ADV7511 supports 1080P 60Hz, YCbCr 4:2:2 encoding via 16-bit input data mapping.”
The HDMI codec circuit is shown in the following figure (figure 1-15 from UG850):
What we can see from this figure is that there are only 16 data pins connected to the ADV7511. Thus, it can be used to output 8-bits YCbCr422.
The Hardware User’s Guide for the ADV7511 can be found on Analog Website:
In this documentation we can see the different configurations in table 5 to table 16. With the connection on the ZC702 (data connected from D8 to D23), we can see that we can use the format presented in table 7 (with style 1,2 or 3).
The ADV7511 needs to be configured using the I2C interface.
As we can see from the following figure (figure 1-16 from UG850), the ZC702 HDMI codec can be programmed using the I2C from the PS (Processing System) or from the PL (Programmable Logic). In our design we will use the I2C from the PS.
The U44 on the figure above is an I2C switch and its address is 0x74. It must be addressed and configured first to select the desired downstream device. We will see this in a next Video Series.
Note: This tutorial is intended to be used only with Vivado 2018.1 and only with the ZC702
Note: A valid license for the Test Pattern Generator is required to build the design.
The block design already has an AXI4-Stream to Video Out IP configured for YUV422 and connected to the Block Design (BD) output and a clocking wizard to generate the video clock.
Note that the project includes a constraints file (ZC702.xdc) containing the pin locations for the design outputs. These constraints are taken from the Appendix C of UG850 (with the pin names changed to match the BD outputs).
In the Run Block Automation window, leave the default parameters (make sure apply board preset is checked) and click OK. This will configure the Zynq for the ZC702 board automatically
If we double click on the Zynq IP to open its configuration GUI, we can see that the I2C interface has been enabled (as well as the UART).
We know from the Video Beginner Series 12 that if we want to connect the TPG to the AXI4-Stream to Video Out IP for YUV422 data, we need to use an AXI-Subset converter in-between
This step will automatically connect the AXI4-Lite interface from the TPG to the Zynq processor and the clocks and resets to the AXI4-Stream Subset converter and the AXI4-Stream to Video Out.
Click Generate on the Generate Output Products pop up window
Once the bitstream is generated, export the Hardware Definition File (hdf) to be used in SDK by clicking on File > Export > Export Hardware…
In the Export Hardware pop up window, enable Include bitstream and click Ok
This will create a .sdk directory with the hdf file inside. We will use this hdf file in the next Video Series
29. Close Vivado