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Adventurer
Adventurer
1,169 Views
Registered: ‎05-28-2018

Video TPG Example project fails to create itself

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When you pull up the Video TPG IP as in pg103-v-tpg.pdf (Ch 6,) by right clicking on the TPG in the sources (step 5,) the scripts that run (specifically v_tpg_0_exdes.tcl) fails when it tries to set_property used_in_simulation false [get_files ex_synth.bd]. The object ex_synth.bd does not exist, and the example creation halts in an unknown state.

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Adventurer
Adventurer
1,062 Views
Registered: ‎05-28-2018

I read some other articles with the subject "IF is not declared under prefix inst," and several mentioned re-installing the tools. So, I downloaded the entire 15.65GB installation, uninstalled and re-installed my Web-pack tools - et voila!

Now, I've been using this same set of tools since May. This DOES NOT instill confidence in your web-install (as opposed to downloading the entire image) process.

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Moderator
Moderator
1,161 Views
Registered: ‎10-04-2017

Hi @gcsimmonsjr,

 

This sounds like a windows path length error, please move your project to a shorter windows path. EX. C:/X/TPG/

For more information see AR-52787.

 

If this is not a path length issue:

  • What OS are you using?
  • What version of the tools? 2018.1? 2018.2?
  • Can you attach the log or the output from the console showing the error?

 

-Sam

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub
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Adventurer
Adventurer
1,149 Views
Registered: ‎05-28-2018

Yes, I tried taking all the spaces out of my Windows path c:\Xilinx\Tutorials\TPG_Example and re-creating the example in THAT directory. It still failed.

C:\Xilinx\Tutorial\TPG_Example\v_tpg_0_ex\v_tpg_0_ex.sim\sim_1\behav\xsim\elaborate.log

Vivado Simulator 2017.4
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2017.4/bin/unwrapped/win64.o/xelab.exe -wto fb63d3397f3142e5bbed7afb1b0b31c9 --incr --debug typical --relax --mt 2 -L axi_infrastructure_v1_1_0 -L smartconnect_v1_0 -L axi_protocol_checker_v2_0_1 -L xil_defaultlib -L axi_vip_v1_1_1 -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_12 -L axi_lite_ipif_v3_0_4 -L v_tc_v6_1_12 -L v_vid_in_axi4s_v4_0_7 -L v_axi4s_vid_out_v4_0_8 -L v_tpg_v7_0_9 -L generic_baseblocks_v2_1_0 -L axi_register_slice_v2_1_15 -L fifo_generator_v13_2_1 -L axi_data_fifo_v2_1_14 -L axi_crossbar_v2_1_16 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot v_tpg_0_exdes_tb_behav xil_defaultlib.v_tpg_0_exdes_tb xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
ERROR: [VRFC 10-93] IF is not declared under prefix inst [c:/Xilinx/Tutorial/TPG_Example/v_tpg_0_ex/imports/v_tpg_0_exdes_tb.sv:66]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.

 

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Adventurer
Adventurer
1,147 Views
Registered: ‎05-28-2018

Looks like it's v_tpg_0_exdes_tb.sv - line 66.

[VRFC 10-93] IF is not declared under prefix inst ["c:/Xilinx/Tutorial/TPG_Example/v_tpg_0_ex/imports/v_tpg_0_exdes_tb.sv":66]

v_tpg_0_exdes_tb.png

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Adventurer
Adventurer
1,063 Views
Registered: ‎05-28-2018

I read some other articles with the subject "IF is not declared under prefix inst," and several mentioned re-installing the tools. So, I downloaded the entire 15.65GB installation, uninstalled and re-installed my Web-pack tools - et voila!

Now, I've been using this same set of tools since May. This DOES NOT instill confidence in your web-install (as opposed to downloading the entire image) process.

View solution in original post