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Scholar
Scholar
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Registered: ‎04-27-2010

Video TPG simulation issue

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I have created a video test pattern generator, and then opened the example design in Vivado 2017.4. When I run the simulation I am getting the following errors. Anyone seen this issue before?

 

ERROR: [VRFC 10-426] cannot find port m_axis_video_TDEST on this module [d:/HDS/hdmi/v_tpg_0_ex/v_tpg_0_ex.ip_user_files/bd/ex_sim/ip/ex_sim_v_tpg_0_0/sim/ex_sim_v_tpg_0_0.v:184]
ERROR: [VRFC 10-426] cannot find port m_axis_video_TID on this module [d:/HDS/hdmi/v_tpg_0_ex/v_tpg_0_ex.ip_user_files/bd/ex_sim/ip/ex_sim_v_tpg_0_0/sim/ex_sim_v_tpg_0_0.v:183]
ERROR: [VRFC 10-426] cannot find port m_axis_video_TLAST on this module [d:/HDS/hdmi/v_tpg_0_ex/v_tpg_0_ex.ip_user_files/bd/ex_sim/ip/ex_sim_v_tpg_0_0/sim/ex_sim_v_tpg_0_0.v:182]
ERROR: [VRFC 10-426] cannot find port m_axis_video_TUSER on this module [d:/HDS/hdmi/v_tpg_0_ex/v_tpg_0_ex.ip_user_files/bd/ex_sim/ip/ex_sim_v_tpg_0_0/sim/ex_sim_v_tpg_0_0.v:181]
ERROR: [VRFC 10-426] cannot find port m_axis_video_TSTRB on this module [d:/HDS/hdmi/v_tpg_0_ex/v_tpg_0_ex.ip_user_files/bd/ex_sim/ip/ex_sim_v_tpg_0_0/sim/ex_sim_v_tpg_0_0.v:180]
ERROR: [VRFC 10-426] cannot find port m_axis_video_TKEEP on this module [d:/HDS/hdmi/v_tpg_0_ex/v_tpg_0_ex.ip_user_files/bd/ex_sim/ip/ex_sim_v_tpg_0_0/sim/ex_sim_v_tpg_0_0.v:179]
ERROR: [VRFC 10-426] cannot find port m_axis_video_TDATA on this module [d:/HDS/hdmi/v_tpg_0_ex/v_tpg_0_ex.ip_user_files/bd/ex_sim/ip/ex_sim_v_tpg_0_0/sim/ex_sim_v_tpg_0_0.v:178]
ERROR: [VRFC 10-426] cannot find port m_axis_video_TREADY on this module [d:/HDS/hdmi/v_tpg_0_ex/v_tpg_0_ex.ip_user_files/bd/ex_sim/ip/ex_sim_v_tpg_0_0/sim/ex_sim_v_tpg_0_0.v:177]
ERROR: [VRFC 10-426] cannot find port m_axis_video_TVALID on this module [d:/HDS/hdmi/v_tpg_0_ex/v_tpg_0_ex.ip_user_files/bd/ex_sim/ip/ex_sim_v_tpg_0_0/sim/ex_sim_v_tpg_0_0.v:176]
ERROR: [VRFC 10-2063] Module <ex_sim_v_tpg_1_0> not found while processing module instance <v_tpg_1> [d:/HDS/hdmi/v_tpg_0_ex/v_tpg_0_ex.ip_user_files/bd/ex_sim/sim/ex_sim.v:321]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.

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Moderator
Moderator
2,212 Views
Registered: ‎11-09-2015

Hi @beandigital,

 

Anyone seen this issue before?

Yes, this is the same issue as in AR#70421. There is a patch for 2017.4 on windows (no issue on linux). If possible, I recommend to move to 2018.1

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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Moderator
Moderator
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Registered: ‎11-09-2015

Hi @beandigital,

 

Anyone seen this issue before?

Yes, this is the same issue as in AR#70421. There is a patch for 2017.4 on windows (no issue on linux). If possible, I recommend to move to 2018.1

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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Scholar
Scholar
2,136 Views
Registered: ‎04-27-2010

I did move to 2018.1, and the simulation now starts. But I dont think its really working as it should. The video stream doesn't do anything. See the image below. I did run it for over 35ms and just the same. 

 

Untitled.png

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Scholar
Scholar
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Registered: ‎03-28-2016

The Video TPG must be initialized and started via the AXI-Lite interface.  The Zynq VIP (DS940) can be helpful for that.

 

Ted Booth | Tech. Lead FPGA Design Engineer | DesignLinx Solutions
https://www.designlinxhs.com
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Moderator
Moderator
2,120 Views
Registered: ‎11-09-2015

Hi @beandigital,

 

You might want to read my Xilinx Video Series. The Video Beginner Series 4 is a simulation with the TPG.

 

Note: The TPG also has an example design which can be simulated (and a more feature than mine). Add the IP to your design. In the source window, right click on the TPG > open example design

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Scholar
Scholar
2,103 Views
Registered: ‎04-27-2010

That is the example design running! Surely it should just work out of the box? 

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Moderator
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Registered: ‎11-09-2015

HI @beandigital,

 

Try to recreate the project from scratch in 2018.1. Do not move the example design from 2017.4 to 2018.1 else you could face the same issue (you would need to make sure that the IP is correctly regenerated).

 

And if you need, you can always try my Video Beginner Series 4 which I know is working ;-)

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Scholar
Scholar
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Registered: ‎04-27-2010

If I open the BD of the example design it has a lot more IP than yours. Microblaze processor, multiple TPG etc. I will probably try yours. Thanks

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Registered: ‎11-09-2015

Hi @beandigital,

 

FYI. The example design has 2 versions: one for synthesis and one for simulation.

 

The one for simulation does not have a microblaze but a VIP. It has 2 TPG IPs, one to use the AXI4-Stream input (pass-through).

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Moderator
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Registered: ‎11-09-2015

Hi @beandigital,

 

Did you make progress with my design?

 

I tried the example design on windows, generated with 2018.1 and I get output from the TPG after 5ms (it is waiting for vsync):

TPG.JPG

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Moderator
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Registered: ‎11-09-2015

Hi @beandigital,

 

This topic is still open and is waiting for you.

If your question is answered or your issue is solved, please mark the response which helped as solution (click on the button "Accept as solution" below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Best Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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