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19adam90
Observer
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Registered: ‎09-29-2018

Video Test Pattern Generator v8.0 - ZedBoard - setup time issue

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Hello,

Based on Xilinx Video Series 19 https://forums.xilinx.com/t5/Video/Video-Series-19-Using-the-On-Board-HDMI-on-ZC702-Vivado-design/td-p/914989, I have created a project for testing a 1080p hdmi output on the ZedBoard.

Generating hardware for Vivado 2018.2 and Video Test Pattern Generator v7.0 IP was succesful with following settings:

video clock for v_tpg, v_tc, v_axis4s_vid_out - 148.5 MHz

axi clock for v_tpg, ps7_axi_periph, v_axis4s_vid_out  - 150 MHz

I have upgraded my project from Vivado 2018.2 to Vivado 2019.2 and Video Test Pattern Generator v7.0 IP to Video Test Pattern Generator v8.0 IP.

Using the same clock settings I am getting setup time error after implementation.

A maximum clock that I can use for axi without errors is 135 MHz.

 

Is this an IP limitation for xc7z020clg484-1 device or maybe a constraints issue?

 

Attached pictures are shows block design and timing implementation results for 148.5 MHz AXI and Video clock configuration.

block_design.pngtiming.pngtiming2.png

 

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florentw
Moderator
Moderator
863 Views
Registered: ‎11-09-2015

Hi @19adam90 

The answers will not be soon. It will be in the next version of the PG.

But a typical max frequency is 150 MHz for an Artix-7 fabric with -2 speedgrade (I am refering to other HLS based IP as the VPSS from pg231).

The Zedboard has a -1 speegrade and the Zynq has a Artix-7 fabric so it is expected that the max frequency would be below 150 MHz. So a 135 MHz max is not to surprising.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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View solution in original post

11 Replies
watari
Teacher
Teacher
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Registered: ‎06-16-2013

Hi @19adam90 

 

Would you share detail report of worst negative slack ?

 

Best regards,

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19adam90
Observer
Observer
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Registered: ‎09-29-2018

Hi @watari ,

 

I am sending print screens from WNS (Path 21) and the Report Timing Summary in a "timing report.txt".

 

Best regards,

 

WNS1.pngWNS2.pngWNS3.png

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watari
Teacher
Teacher
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Registered: ‎06-16-2013

Hi @19adam90 

 

I made sure your timing report file.

The route causes are location issue (*1) and high fanout issue (*2)

So, I suggest you to change synthesis and implementation strategies.

Refer the following pdf on page 35.

 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug904-vivado-implementation.pdf

 

*1)

BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r Z_system_i/clk_wiz_1/inst/clkout1_buf/O
net (fo=2991, routed) 1.635 1.638 Z_system_i/v_tpg_0/inst/v_tpg_CTRL_s_axi_U/ap_clk
SLICE_X39Y74 FDRE r Z_system_i/v_tpg_0/inst/v_tpg_CTRL_s_axi_U/int_bck_motion_en_reg[3]/C

 

*2)

select_ln1161_reg_618[31]_i_5/O
net (fo=63, routed) 0.911 4.995 Z_system_i/v_tpg_0/inst/tpgBackground_U0/

 

Best regards

19adam90
Observer
Observer
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Registered: ‎09-29-2018

Hi @watari ,

I have checked all synthesis and implementation strategies and some combinations of them.

Unfortunately, without any success.

Results are below in the tables.

I am wondering why upgrading version of the v_tpg is causing intra_path timing fail 150 MHz clock.

Maybe it is connected with added compatiblity for higher resolutions...

My conclusion a this moment is that is not possible to use 100% effectively this IP with a clock higher than 135 Mhz in case of my design (which is basically very simple).

However older version (7.0) was working without any timinig problem.

Do you have any ideas or reccomendations?

 

(For tests I had changed axi clock for FCLK=150MHz video clock is 148.5 MHz)

Analysis strategySynthesis strategyWNSTNSNumber of failing endpoints
Vivado Synthesis DefaultsFlow_Quick-3.716-1960.751407
Vivado Synthesis DefaultsFlow_RuntimeOptimized-0.983-42.49754
Vivado Synthesis DefaultsArea_ExploreWithRemap-0.709-19.01550
Vivado Synthesis DefaultsArea_ExploreSequential-0.591-21.67355
Vivado Synthesis DefaultsArea_Explore-0.568-25.2559
Vivado Synthesis DefaultsPower_DefaultOpt-0.557-20.32155
Vivado Synthesis DefaultsCongestion_SpreadLogic_medium-0.512-18.11254
Vivado Synthesis DefaultsPerformance_Retiming-0.504-15.93154
Vivado Synthesis DefaultsPower_ExploreArea-0.496-14.71254
Vivado Synthesis DefaultsCongestion_SpreadLogic_low-0.484-10.05646
Vivado Synthesis DefaultsPerformance_RefinePlacement-0.466-7.8522
Vivado Synthesis DefaultsPerformance_WLBlockPlacementFanoutOpt-0.465-10.05742
Vivado Synthesis DefaultsPerformance_Explore-0.464-7.79122
Vivado Synthesis DefaultsVivado Implementation Defaults-0.456-14.37154
Vivado Synthesis DefaultsCongestion_SpreadLogic_high-0.451-13.58254
Vivado Synthesis DefaultsPerformance_WLBlockPlacement-0.447-18.37754
Vivado Synthesis DefaultsPerformance_ExploreWithRemap-0.441-10.04848
Vivado Synthesis DefaultsPerformance_NetDelay_low-0.433-17.89254
Vivado Synthesis DefaultsPerformance_ExplorePostRoutePhysOpt-0.42-6.83722
Vivado Synthesis DefaultsPerformance_NetDelay_high-0.402-7.68454
Vivado Synthesis DefaultsPerformance_ExtraTimingOpt-0.38-12.42254
Vivado Synthesis DefaultsCongestion_SSI_SpreadLogic_low-0.363-5.58122
Vivado Synthesis DefaultsPerformance_SpreadSLLs-0.362-5.56222
Vivado Synthesis DefaultsPerformance_BalanceSLLs-0.362-5.56222
Vivado Synthesis DefaultsPerformance_BalanceSLRs-0.362-5.56222
Vivado Synthesis DefaultsPerformance_EarlyBLockPlacement-0.354-5.37522
Vivado Synthesis DefaultsCongestion_SSI_SpreadLogic_high-0.347-5.22122
Vivado Synthesis DefaultsFlow_RunPhysOpt-0.329-4.82722
Vivado Synthesis DefaultsFlow_RunPostRoutPhysOpt-0.311-4.4422
Vivado Synthesis DefaultsPerformance_HighUtilSLRs-0.275-8.212

54

 

Analysis strategySynthesis strategyWNSTNSNumber of failing endpoints
Vivado Synthesis DefaultsVivado Implementation Defaults-0.456-14.37154
Flow_AreaOptimized_highVivado Implementation Defaults-0.456-14.37154
Flow_AreaOptimized_mediumVivado Implementation Defaults-0.456-14.37154
Flow_AreaMultThresholdDSPVivado Implementation Defaults-0.456-14.37154
Flow_AlternateRoutabilityVivado Implementation Defaults-0.456-14.37154
Flow_PerfOptimized_highVivado Implementation Defaults-0.456-14.37154
Flow_PerfThresholdCarryVivado Implementation Defaults-0.456-14.37154
Flow_RuntimeOptimizedVivado Implementation Defaults-0.456-14.37154

 

Analysis strategySynthesis strategyWNSTNSNumber of failing endpoints
Flow_PerfOpitmized_highFlow_RunPostRoutePhysOpt-0.311-4.4422
Flow_AlternateRoutabilityFlow_RunPostRoutePhysOpt-0.311-4.4422
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florentw
Moderator
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Registered: ‎11-09-2015

Hi @19adam90 

If you check my video series, I believe I have disabled some pattern in the TPG configuration to ease timing. You might want to do the same and disable all the pattern which you are not going to use to ease the timing


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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19adam90
Observer
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Registered: ‎09-29-2018

HI @florentw ,

Thank you for reply.

I will check different configurations and post the results.

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19adam90
Observer
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Registered: ‎09-29-2018

@florentw@watari 

I checked different pattern configurations.

Results below shows that "ZONE PLATE" is pattern which leads to the internal_path timing problem.

So disabling "ZONE PLATE" pattern and use of another implementation strategy is the solution of my problem, but I am still wondering why same configuration with older v_tpg IP version (7.0) can be implemented with all of the patterns and default synthesis and implementation strategies.

Is it any way in the Vivado 2019.2 with the v_tpg 8.0 to implement this design?

I am supposing that newer version of the IP is more optimzed than older one but in this case it looks opposite...

Analysis strategySynthesis strategyWNSTNSNumber of failing endpointsv_tpg patterns
Flow_PerfOptimized_highFlow_RunPostRoutePhysOpt-0.311-4.4422all enabled
Flow_PerfOptimized_highFlow_RunPostRoutePhysOpt0.39900SOLID COLOR - only one enable
Flow_PerfOptimized_highFlow_RunPostRoutePhysOpt0.70500RAMP - only one enable
Flow_PerfOptimized_highFlow_RunPostRoutePhysOpt0.68100DISPLAY PORT - only one enable
Flow_PerfOpitmized_highFlow_RunPostRoutePhysOpt0.01400COLOR BAR - only one enable
Flow_PerfOptimized_highFlow_RunPostRoutePhysOpt0.75500COLOR SWEEP - only one enable
Flow_PerfOptimized_highFlow_RunPostRoutePhysOpt-0.485-8.16322ZONE PLATE - only one enable
Flow_PerfOptimized_highFlow_RunPostRoutePhysOpt0.00800COLOR BAR, FOREGROUND
Flow_PerfOptimized_highFlow_RunPostRoutePhysOpt0.09100SOLID COLOR, RAMP, COLOR BAR, DISPLAY PORT, COLOR SWEEP, FOREGROUND
Flow_PerfOptimized_highFlow_RunPostRoutePhysOpt-0.371-5.7322ZONE PLATE, FOREGROUND
Flow_PerfOptimized_highFlow_RunPostRoutePhysOpt-0.468-16.88154SOLID COLOR, RAMP, COLOR BAR, DISPLAY PORT, COLOR SWEEP, ZONE PLATE
Vivado Synthesis DefaultsVivado Implementation Defaults-0.144-2.79323SOLID COLOR, RAMP, COLOR BAR, DISPLAY PORT, COLOR SWEEP, FOREGROUND
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florentw
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Registered: ‎11-09-2015

HI @19adam90 

This is difficult to say. I was already seeing timing failure with the TPG v7.0. So this might also be coming from your design . The more you have in your design the harder it is to meet timing. And maybe the new generated code of the TPG expose more the issue.

I recommend you to disable the zonne plate or to increase the pixels per clock configuration of the TPG which will help to meet timing.

On my side, I have requested the development team of the TPG to better document what max frequencies are supported for which configuration.

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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19adam90
Observer
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Registered: ‎09-29-2018

Hi @florentw ,

I would be appreciated if you post your answer from the development team of TPG.

Best regards

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florentw
Moderator
Moderator
864 Views
Registered: ‎11-09-2015

Hi @19adam90 

The answers will not be soon. It will be in the next version of the PG.

But a typical max frequency is 150 MHz for an Artix-7 fabric with -2 speedgrade (I am refering to other HLS based IP as the VPSS from pg231).

The Zedboard has a -1 speegrade and the Zynq has a Artix-7 fabric so it is expected that the max frequency would be below 150 MHz. So a 135 MHz max is not to surprising.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

19adam90
Observer
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Registered: ‎09-29-2018

@florentw @watari 

Thank you all for help in this matter.

 

Best regards

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