06-29-2020 05:54 AM
Hi Team,
Whether application development is required for the proper working of video test pattern generator or hardware block design is sufficient.
how we can develop, which library files need to include for development.
with regards,
Ratheesh.
06-29-2020 09:11 PM
Hello @Ratheesh ,
Could You please go through the Video Series 21, Which is a TPG Application Implemented on ZC702. Hope this design will clear all Your concerns regarding this IP.
With Regards,
Ashok.
06-29-2020 09:11 PM
Hello @Ratheesh ,
Could You please go through the Video Series 21, Which is a TPG Application Implemented on ZC702. Hope this design will clear all Your concerns regarding this IP.
With Regards,
Ashok.
06-30-2020 12:11 AM
Hi @Ratheesh
If you are good in Vivado HLS design, then you can create fixed video test pattern generator IP, for example, IP will not have axi_lite interface and will work for definite resolution only.
Then after, it will no longer require application development but hardware block design will be sufficient. For creating custom video test pattern generator IP, you can go through Video Series 14 and Video Series 15 .
On the other hand, if you use Xilinx video test pattern generator, then you must follow as @ashokkum says.
Kind Regards,
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06-30-2020 02:00 AM
HI @Ratheesh
There is another option than the ones mentioned by @Nikhil_Thapa and @Ratheesh
You can generate the AXI4-Lite transactions from your HW design. Either by creating your own IP or by using a AXI traffic generator.
The TPG IP is quite basic IP and does not really require the use of the driver. Thus few AXI4 transactions will be enough to get it running