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Visitor
Visitor
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Registered: ‎02-22-2018

Video Timming Controller problems

Hi. I'm having several problems with the video timming controller component. On one side, the video timming controller in Detector mode is not able to get locked to a video signal. On the other side, the AXI4 to video component is not able also to get locked, and I think in this case the problem is because the Video Timming Controller in Generation mode is not synchronised to the input video signal.

 

Here below the exact problems :

 

1) Video timming controller in detector mode: Having a video signal, I've configured this block in order to detect video by using DE, HSYNC and VSYNC. On the other hand, I've connected the INTC_IF(8) to the video IN TO AXI4 block. The problem is the Video Timming Controller in Detector mode never gets locked. I've tried to invert HSYNC and VSYNC signals because in some thread I've read the video Timming Detector doesn't really detect their polarity, but with no success.

 

In order to try to find the reason of this issue, I've included in my design a Video Timming Controller in Generation mode, and I've connected its output to my Detector input. Again, I've never been able to get synchronization in the detector block.

 

2) AXI4 to video and Video Timming Controller in Generator mode: I'm not able to get it locked and I'm stuck here from more than one week. What I think is that the AXI4 to video block is not correctly synchronized to the video input. I've tried to configure it in slave and master, but same result.

 

In order to try to find the reason of this problem, I've connected the VIDEO_IN_TO_AXI4 directly to the AXI4_TO_VIDEO block. 

The only thing I've detected is that sometimes, the AXI4_TO_VIDEO_TREADY signal gets to low level, so the VIDEO_IN_TO_AXI4 stops to insert video into the block. Check screenshot about this issue.

 

If you need, I could include sections of code in order to make easier to understand these issues.

 

Any help would be welcome. Regards,

 

Eduardo

AXI4_TO_VIDEO.png
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Moderator
Moderator
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Registered: ‎11-09-2015

Hi @ardoster,

 

You might want to start only with the generation (use a test pattern generator) and make sure this work. Then move to the detection part.

It will be easier to debug step by step.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Visitor
Visitor
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Registered: ‎02-22-2018

Hi

 

Thanks for your answer. I've been making several tests.

 

1. I've connected a video timming controller generator to an video timming controller detector, but the detection block still is not able to lock. The generator block generates correctly all signals.

 

2. By using the same previous example, i've connected the following chain in order to emulate video input.

 

VTC Generator -> Video to AXI4 (bayer) -> AXI4 to video (connected to another VTC generator)

 

And everything looks correct. The problem now is that when I replace the first VTC generator by my video signal, the AXI4 to video block stops to get lock. I can't see the reason about this because this VTC block is emulating exactly the same input video signal.

 

In the attached file, you can find the project example I'm using for these tests.

 

Any help would be welcome.

 

Regards,

 

Eduardo

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Moderator
Moderator
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Registered: ‎11-09-2015

Hi @ardoster,

 

The problem now is that when I replace the first VTC generator by my video signal, the AXI4 to video block stops to get lock. I can't see the reason about this because this VTC block is emulating exactly the same input video signal.

-> Are you sure it is exactly the same signals? I would make sure that you are not changing the data signals while data enable is not high and I would also ensure that the vsync and hsync are really high when expected.

Also do you have as many inputs with your video signal as with the VTC?

Also are you seeing data on the AXI4S interface? If not, is it because you do not have tvalid or tready high?

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Visitor
Visitor
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Registered: ‎02-22-2018

Hi. Thanks again. I'm pretty sure the emulated signals and the actual video signals are exactly the same. But it is evident that i'm commiting some mistake. The problem in my case is I don't know what's wrong.

 

Attached, you can find 4 screenshots: The 2 first, corresponds to the emulated signal. The other 2 screenshots correspond to the actual video signal.

 

Both waveforms (emulated and real) corresponds to different designs, where the only difference beween them is the video source (emulated or real).

 

Any comment would be welcome.

 

Regards,

 

Eduardo

 

vtg_sim_1.png
vtg_sim2.png
real_1.png
real_2.png
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Moderator
Moderator
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Registered: ‎11-09-2015

HI @ardoster,

 

You seem to be looking only at one line.

 

You should make sure about the time between 2 hsync and 2 vsync is correct.

 

I am not familiar with the VTC in ISE but do you have the AXI4-lite interface enabled? If it is the case, did you look at the registers to see if you have more information?

Else, are you looking at the value of the intc_if output?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Visitor
Visitor
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Registered: ‎02-22-2018

Dear Florent

 

Thanks for your help. The problem was the VSync signals were not exactly the same. I'm almost sure I checked them, but after some change they should change. Not sure about that.

 

Anyway, I'm still having problems with whe Video Timing Controller in Detection mode. I've attached my example project about this point several posts above. Briefely: I'm not able to lock the video timing detector, even connecting its input to the output of a different video timming controller in generation mode.

 

Any comment would be welcome.

 

Regards,

 

Eduardo

 

 

 

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Moderator
Moderator
3,282 Views
Registered: ‎11-09-2015

Hi @ardoster,

 

You might want to read this topic from @toshas, he made some good analysis on the VTC as detector:

https://forums.xilinx.com/t5/Video/Is-timing-detection-in-VTC-core-broken/td-p/810055

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Visitor
Visitor
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Registered: ‎02-22-2018

Thanks Florent, and sorry the delay to reply you, but I couldn't do it before.

 

Yes, I had already read that thread, but I think that's not my case. In my case, I'm connecting directly a VTC generator to a VTC detector, so signals should be already correct. In the thread you are referring, the problem was the polarity of hsync and vsync signals, which are not detected automatically although in the datasheet is possible to read "Automatic detection of input video control signal polarities" (why don't you correct or clarify this sentence in the datasheet???!!!). Anyway, I've checked this with all possible combinations of vsync and hsync, and active_video polarities with no success: VTC detector never gets lock.

 

Any other suggestion would be welcome.

 

Thanks in advance. Regards,

 

Eduardo

 

 

 

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Moderator
Moderator
3,244 Views
Registered: ‎11-09-2015

HI @ardoster,

 

Did you include the INTC interface? If yes, what is the value of intc_if?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Visitor
Visitor
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Registered: ‎02-22-2018

Florent, thanks again for your help.

 

INT_IF signal is changing between 0x00000E6B and 0x00000E7B. Attached screenshot below.

 

Reading the datasheet, these are the enabled bits:

 

  • VBlank_Lock = TRUE (VBlank and HBlank are not connected, only VSync, HSync and Active Video)
  • HBlank_Lock = TRUE
  • VSync_Lock = FALSE
  • HSync_Lock = TRUE
  • Active Video Lock = TRUE before VSync rising edge. FALSE after it
  • Active Chroma Lock = TRUE (Active Chroma is not used)
  • Bit 6: Datasheet says this bit is not used and its value should be 0, but its value is 1.

 

  • LOCK = FALSE (not locked)
  • LOCK_LOSS = TRUE
  • DET_VBLANK = TRUE
  • DET_ACTIVE_VIDEO = TRUE

What I see is the problem is VSync, but because the input to this block is the VTC Generator output, I don't see the reason to this fail. It is supossed generated signal should be correct.

 

What am I missing? Thanks again.

 

Eduardo

new_vtc.png
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Moderator
Moderator
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Registered: ‎11-09-2015

Hi @ardoster,

 

How are you configuring the generator?

Is it a preset resolution? If yes, which resolution?

Did you try another resolution?

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Visitor
Visitor
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Registered: ‎02-22-2018

Hi @florentw

 

I've attached my used configuration. It is not a standard resolution (1440x1080). The values I'm using are the values I need to replicate my input video signal. 

 

By the way, when using a more standard resolution looks right. But in this case, I don't understand: some resolutions are ok and other not??? It is not the same block?

 

Thanks again

 

Eduardo

vtc_config.png
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Moderator
Moderator
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Registered: ‎11-09-2015

Hi @ardoster,

 

Where does you custom resolution comes from? Is it from any video spec? Are you sure the synchronization signals are long enough? Are you sure about their polarity?

 

I guess this is the reason why the detector is not working.

 

Regards,

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Visitor
Visitor
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Registered: ‎02-22-2018

Thanks for your reply @florentw

 

My actual video source is a CCD sensor. Its signals corresponds exactly to this emulated signal generated by my VTC block in generation mode. I'm pretty sure about this point because I checked it at first of this post. In addition, Video IN to AXI4 block is able to work with these signals, and the AXI4_TO_VIDEO block also is working correctly with these emulated signals.

 

The only block is not able to work is the VTC block in detector mode. Ironically, this block is supossed it should detect the input video signal? 

 

The Video Timing Controller core supports detecting video frame sizes up to 8192 clocks by
8192 lines (including horizontal and vertical blanking). The Video Timing Controller core
automatically detects the timing involved with horizontal/vertical blanks and syncs. The
timing of the active_video and the active_chroma signals are also detected. This allows the
user to easily determine the video frame size via the core register (AXI4-Lite) interface.

 

On the other hand, I've tested all possible combinations of polarities between HSYNC / VSYNC and VIDEO_ACTIVE signals.

 

If you wish, attached to this post you can find my source code.

 

Thanks again for your help and patience. Any help is welcome.

 

Regards,

 

Eduardo

 

 

 

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Moderator
Moderator
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Registered: ‎11-09-2015

HI @ardoster,

 

The AXI4-Stream to video is not really telling you that your timing is correct. It will only tell you that it has enough data related for the timing. So it does not mean that the timing generated by the generator is correct. It would be interesting to see if this timing works with a monitor.

 

You need to have all the correct polarity but also the hsync/vsync/hblank and vblank should happen at a certain time and for a certain time. If incorrect, the VTC might not lock. Which is your case.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Visitor
Visitor
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Registered: ‎02-22-2018

Dear @florentw

 

Thanks for your help. The only thing I've been able to veriffy these last days is that the output video is played correctly. VTC detector is istill not able to get locked.

 

Thanks again

 

Eduardo

 

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Moderator
Moderator
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Registered: ‎11-09-2015

Hi @ardoster,

 

"is that the output video is played correctly"

What do you mean? Did you plugged a monitor? Please clarify


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Visitor
Visitor
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Registered: ‎02-22-2018

Hi @florentw

 

I'm sorry: The video output is connected to an IMX6 processor which implements a video streaming server. I'm able to see the video output when I connect to this video stream by using VLC or any other similar player. For this test: i'm able to see the test data I'm emulating in my test project by using the VTC generator, and when using the actual sensor output, I'm able to see the image is being captured by the CCD sensor. In both cases, the video is being played correctly, but the VTC detector is not working still.

 

These tests would be sufficient as prove that my video chain and the video signals i'm inserting and/or emulating should be correct. 

 

 

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Explorer
Explorer
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Registered: ‎07-18-2011

I don't know if this will create a problem or not, but I noticed your generator vertical sync starts at line 1080. which is the same as your end of active vertical.   This gives you no vertical front porch,  a one-line vertical sync, and 50 lines of vertical back porch, which may upset the VTCs vblanking detection. 

 

Try moving the vsync start to line 1081  and vsync end to line 1082, to give you a one-line front porch and one line vsync, or try adjusting it for a couple of lines of each.

Visitor
Visitor
3,238 Views
Registered: ‎02-22-2018

Thanks for your reply @reaiken

 

I know what you say, and I tried too. Anyway I've just checked it again, but same result :-(

 

Thanks for your help

 

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Moderator
Moderator
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Registered: ‎11-09-2015

Hi @ardoster,

 

Could you try with the following setting for the generator (following VESA CVT spec):

vtc2.PNG

 

I have tried in simulation Generator -> detector and I am able to lock with 1440x1080:

vtc.PNG

 

So I still think the issue is coming from your timing signals.

 

Note 1: In my test, I haven't enabled the hblank and vblank signals but I do not think this is an issue.

Note 2: I have used vivado 2017.4 (so VTC v6.1 rev.12)

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Visitor
Visitor
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Registered: ‎02-22-2018

Dear @florentw

 

Thanks for your reply. I've just tested your values and effectively, the VTC Detector is able to lock. The problem is those values are not the values my CCD image sensor is producing. 

 

I've chosen my values because those values are the values I need to replicate the signal I'm receiving from my image sensor. I could assume the problem is my timing signals, but in that case, what's wrong with my signals? Video_to_axi4 or AXI4_to_video blocks are able to work with them. And during these days I've verified that if this information is not correct, these blocks are not able to work.

 

Thanks again

 

 

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Moderator
Moderator
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Registered: ‎11-09-2015

Hi @ardoster,

 

I could assume the problem is my timing signals, but in that case, what's wrong with my signals? Video_to_axi4 or AXI4_to_video blocks are able to work with them. And during these days I've verified that if this information is not correct, these blocks are not able to work.

Again, the Video_to_axi4 or AXI4_to_video are not a reference for timing signals. The just check that there is enough data and that the signals are correct for the frame (ex: you your data enable is longer than the frame size or for a line).

The issue with your signals might be the length of your blanking or the time when the sync is happening. However, in my opinion it is not an issue with the VTC.

 

Also you might want to set 1440 for the 4 horizontal fine ajustemt values and 1 line for vsync might be short...

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Visitor
Visitor
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Registered: ‎02-22-2018

Thanks @florentw

 

Just to clarify: I'm not really interested in a VTC detector working against a VTC generator: what I really want is the VTC detector works against my sensor image. But because I can't send you my HW and my CCD image, this project test is the only way to provide you an easy way to demonstrate the VTC detector is not able to sync against my signals. I will check all again, but VTC generator is replicating the signals and timmings I get from the sensor. I could change the parameters in the VTC generator, but this will not modify the signals and timmings I get from the sensor. And because the rest of the chain is working correctly, in my opinion there's a problem with the VTC detector.

 

In order to try to fix it, do you have a list of requirements the signals must fit? Maximum lengths? Minimum lengths? In the datasheet I can't find this information.

 

Thanks again

 

Eduardo

 

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Moderator
Moderator
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Registered: ‎11-09-2015

Hi @ardoster,

 

And because the rest of the chain is working correctly, in my opinion there's a problem with the VTC detector.

We are not sharing the same point of view. I have shown you that with standard video timing signals, the VTC detector is working. So for me it is an issue with your timing signals and with the sensors if not following common timing signals.

 

In order to try to fix it, do you have a list of requirements the signals must fit? Maximum lengths? Minimum lengths? In the datasheet I can't find this information.

Note this is not from the VTC. I have used VESA CVT timing signals, which is commonly used with video equipments (as monitors or GPU). So there is not specific reason to be in the VTC datasheet.

 

If I found the folowing link googling:

https://wiki.osdev.org/Video_Signals_And_Timing

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
Moderator
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Registered: ‎11-09-2015

Hi @ardoster,

 

Do you have any updates on this? If everything is clear for you, please kindly close this topic by marking the best reply as accepted solution.

 

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Visitor
Visitor
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Registered: ‎02-22-2018

Hi

 

I'm still having the same problems, so I can't consider any reply as solution. But because I'm locked at this point I've decided to work on other areas of the project. In my opinion, VTC detector should be able to work with non-standard video inputs. If this is not the case, it should be clarified on the documentation. Once I'm free again I'll retake this point.

 

Thanks for your help

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Moderator
Moderator
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Registered: ‎11-09-2015

Hi @ardoster,

 

I think you are still missing my main point. The VTC should be able to work with timing signals which is not following a spec but the timing signals need to follow the rules for video timing.

 

Just take the example for a VGA signal. You only have the data + hsync + vsync (no data enable signal):

image005.png

 

If you are not following some kind of rules for hsync and vsync (and blanking period), how do you want the sink yo know the actual size of the frame?

And this is the main purpose of the VTC as detector, to detect the size of the frame. I have used a standard timing because I know it is working. Some other values might work but it needs to be into the "rules" for video signals.

 

Hope this clarifies now.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
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Registered: ‎11-09-2015

HI @ardoster,

 

Any updates on this?

 

Thanks,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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