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leoleonis
Observer
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Registered: ‎07-15-2019

Video-and-Audio/MIPI-D-PHY-RX-asyncrounus

https://forums.xilinx.com/t5/Video-and-Audio/MIPI-D-PHY-RX-asyncrounus/m-p/1207544#M36811

 

the question relies to the thread above, but I was not able to close, save there my last question, so I try it with a new one:

so again: I do the 1byte alignment in the receiver, I use the rxsynchs signal for that - that's all o.k. now.
I understand that the DPHY Core handles each lane independently, as it is written in the MIPI DPHY specification.

however there are some "older" csi2 receivers (1Gbit/sec, no deskew) used by our customers, or other companies, like toshiba. this receivers need aligned lanes, meaning that the SoT Pattern is starting on the same highspeed clock edge on each lane. Therefore we designed our transmitter for aligned lanes to enable this receivers to receive.

I build my receiver for a component verification purpose - we need to find out while testing, if Lanes in our transmitter are aligned.

in older receiver versions I build the DPHY-Core (as well as the receiver) with a serdes by by own. with this, a test of alignment was possible.

with the DPHY-Core from xilinx It's not. 
My question (final) question is, if this is true, and if you could suggest an other solution?
thank you, 
Leo

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karnanl
Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @leoleonis 

>however there are some "older" csi2 receivers (1Gbit/sec, no deskew) used by our customers, or other companies, like toshiba.
>this receivers need aligned lanes, meaning that the SoT Pattern is starting on the same highspeed clock edge on each lane.
>Therefore we designed our transmitter for aligned lanes to enable this receivers to receive.
>I build my receiver for a component verification purpose - we need to find out while testing, if Lanes in our transmitter are aligned.

I see.

>with the DPHY-Core from xilinx It's not.
>My question (final) question is, if this is true, and if you could suggest an other solution?

Yes, your understanding is correct.
Using Xilinx MIPI D-PHY RX IP, you may see skew between data-lanes output data even if transmitter data are aligned.
This behavior is mentioned in PG202.
MIPI_DPHY_does_not_perform_byte_alg.png

# I am not familiar with XAPP1315, but please do check the doc to see if this XAPP is suitable for your application.
     https://www.xilinx.com/support/documentation/application_notes/xapp1315-lvds-source-synch-serdes-clock-multiplication.pdf
   Basically multi lane synchronous use case need some training pattern to align at the start of data sequence.
   Perhaps MIPI D-PHY SoT can be used too.

Regards,
Leo K

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leoleonis
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Registered: ‎07-15-2019

using the ISERDES with a lvds source would be a solution I had before, on the 7series FPGA. However, with this solution I will not be ready for 2Gbit/s and for automatic deskesw, right?

I think I will not be able to split or multiplex the Input-Ports between DPHY and another ISERDES, am I? 
thank you, Leo R

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karnanl
Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @leoleonis 

>I think I will not be able to split or multiplex the Input-Ports between DPHY and another ISERDES, am I?

Yes, your understanding is correct. This is not possible.

>However, with this solution I will not be ready for 2Gbit/s and for automatic deskesw, right?

Not sure if XAPP1315 can support automatic deskew.
For sure , you need to use MIPI CSI-2 RX Subsystem IP to compensate MIPI D-PHY data lanes skew.

If there are "old csi2 receivers"  which cannot align data-lanes using SoT pattern, I think these "old csi2 receivers" are not following MIPI CSI-2 specification/requirement.

Kind Regards,
Leo

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