Video frame looks orders were changed (NTSC with 2VDMA)

[jinhanharu]

Hello guys,

I designed NTSC(RS170) video output (1280 X 480 resolution and 30Hz frame rates, pclk 24.54MHz with 2 VDMA

but the result is poor when I moved the camera, it sometimes(frequently) looks video frame orders are changed(video looks vibrated) but sometimes ok.

in my design,(VIVADO 16.3)

1. input image(1280 X 480, mono 16bit, 40MHz, 30Hz)

2. vid2axi4s : changed to axis

3. vdma1 : to change pclk from 40M to 49.08MHz

- frame buffer : 3

- write channel option : fsync(s2mm tuser), genlock(Dynamic Master), allow unaligned transfers checked

- read channel option : fsync(none), genlock(Dynamic Slave), allow unaligned transfers checked

4-1. vdma 2 : to output interlaced video, with 24.54MHz

- frame buffer : 4

- write channel option : fsync(s2mm tuser), genlock(Dynamic Slave)

- read channel option : fsync(none), genlock(Dynamic Master)

4-2. VTC : timing generator

5. axi4s2vidout : NTSC output

SDK VDMA REGISTER SET

FrameDelay = 0;

EnableCircularBuf = 1;

EnableSync = 1;

PointNum  = 0;

EnableFrameCounter = 0;

FixedFrameStoreAddr = 0;

I tried to resolve this issue like below but I couldn't get the good result

1. change set the both or one of vdma set(dynamic genlock to genlock)

2. change set the VDMA2 channel option

 - Read(Dynamic Slave), Write(Dynamic Master)

3. increasing frame buffer (VDMA1 : 3 to 6,  VDMA2 : 4 to 8)

4. all vdma allow unaligned transfers checked

5. all vdma allow unaligned transfers unchecked

[samk]

Hi @jinhanharu,

My first thought is that something is wrong with how you are using genlock with the interlaced VDMA core, but I need some more information.

Can you provide a screenshot of your block design?

Can you provide a screenshot of the VDMA core that is doing the interlacing?

What are you setting the vsize, hsize, and stride register values to?

Also is there any backpressure in your system?  (ready signals going low)

Do any of your cores report any overflow?

Regards,

Sam

[florentw]

Hi @jinhanharu,

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" buton below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,

[jinhanharu]

Sorry, I was off from my office so I could't check email and community.

I'll feed back what you want soon

[jinhanharu]

Hello, thanks and sorry, Samk

Can you provide a screenshot of your block design?

=> please check attachments below

=> for NTSC serration1,2 pulses(for distingushing even and odd frames) I put the sync generator I designed

=> image is ok , but freqeuntly image delayed when moved image ( I think it looks frame buffer number-time order is changed)

Can you provide a screenshot of the VDMA core that is doing the interlacing?

=> please check attachments below

 VDMA1(main_axi_vdma_60Hz, the name 60 is my mistake , real frame rate is 30Hz) 

- for changing the pixel clock 40M to 49.08MHz (30Hz)

- frame buffers : 3

- write channel option is s2mm tuser, dynamic master

- read channel option is none, dynamic slave

- allow unaligned transfers are checked

VDMA2(main_axi_vdma_60i, the name 60 is my mistake , real frame rate is 30Hz)

- for interlacing output

- frame buffers : 4

- write channel option is s2mm tuser, dynamic slave

- read channel option is none, dynamic master

What are you setting the vsize, hsize, and stride register values to?

VDMA1(main_axi_vdma_60Hz, the name 60 is my mistake , real frame rate is 30Hz) 

- vsize:1280*2

- hsize : 480

- write stride : 1280*2

- read stride : 1280*2

VDMA2(main_axi_vdma_60i, the name 60 is my mistake , real frame rate is 30Hz)

- vsize:1280*2

- write hsize : 480 / read hszie : 240

- write stride : 1280*2

- read stride : 1280*2*2

Also is there any backpressure in your system?  (ready signals going low)

=> video fsync (s2mm tuser option)

=> when system booted, sdk vdma set and vdmas doesn't stop

=> sorry, I can't understand what you want exactly

Do any of your cores report any overflow?

 => No, I don't have the fcn

[samk · Accepted solution]

Hi @jinhanharu,

There is a simpler way to accomplish what you are trying to do. I believe that you only need 1 VDMA and not 2 which will simplify your design. The issue that you are seeing is possibly an issue with the first VDMA and the frame buffering with gunlock enabled.

Please see THIS thread which has an attached example on how to convert progressive video to interlaced video.

Regards,

Sam

[jinhanharu]

Hi @samk

Thank you for your kind answer

I think your help is useful and I'll try and feed back

thank you again