02-19-2020 07:34 AM - edited 02-20-2020 01:49 AM
Hope you all are fine,
I downloaded Digilent/Zybo-Z7-20-HDMI from https://github.com/Digilent/Zybo-Z7-20-HDMI
I have upgraded the ip's, it was displaying output on monitor. Then I have created the ip of sobel edge detection and added the ip in block diagram. After solving some clocking issues, bitstream has been generated. After launching to sdk, when I Launch on Hardware (System Debugger), output doesn't display.
Below is block diagram, please guide me
02-19-2020 08:40 AM
Simulate and see where its failing.
02-19-2020 09:01 AM - edited 02-19-2020 09:10 AM
You might ask this question in the Digilent forum as it is their design and they might be able to GUESS a reason/s.
Just looked into the repo...
Can you control the design functions via TeraTerm?
Did you try option "3/4 - Store one of two test patterns in the chosen video frame buffer"?
Seems like there is a test pattern gen inside the design. If HDMI data stream from PC is not working they use the internal pattern gen.
If nothing works, I would recommed to initially do the HDMI Pass-through project. In this no procesing is done (there are just some internal signal conversions) on the HDMI data. It just tests that your HDMI source and sink are working properly in hardware and you can display a HDMI stream.
02-20-2020 01:40 AM - edited 02-20-2020 01:42 AM
03-02-2020 04:18 AM
Just refer to
and try to find where in you design this is failing. Probably you IP is not able to deliver enough data to keep up with the stream. You might want to consider adding a VDMA or Video frame buffer to reduce the pressure.
03-03-2020 12:00 AM