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murali_2
Visitor
Visitor
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Registered: ‎03-31-2021

Vivado 2020.2 HLS module synthesis

I am trying to synthesis a Vivado project on 2020.2. In the Block design, it fail to synthesis TPG-block. The error log says:

command 'ap_source' returned error code

I've synthesised this TPG block fine on 2019.2 previously.

Is there any workaround for this?

 

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ashokkum
Moderator
Moderator
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Registered: ‎04-09-2019

Hi @murali_2 ,

Have you checked, about the path length limitation for windows platform as addressed in the AR#52787. If you are pretty sure that it is not related to the path length issue, can you add the error details (or) synthesis log details to this thread, which helps to us to debug this issue furtherly.

With Regards,

Ashok.

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murali_2
Visitor
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Registered: ‎03-31-2021

Hi @ashokkum,

Thanks for your reply, I missed to add my OS on the original question, I was doing this in Linux (Ubuntu)

"sudo apt-get install libc6-dev-amd64"

As suggested on:

https://forums.xilinx.com/t5/Design-Entry/Launch-Vitis-HLS-failed-while-synthesizing-VFBW-IP/td-p/1224085

 

Sorted my issue.

 

Murali

 

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