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wadelius
Participant
Participant
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Registered: ‎05-04-2018

Vivado MIPI ip

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Hi, Forum.

I'm about to start a new design and planning to use the Ultrascale+ ZU5 EG or EV.

I have seen a nice dev.kit ZCU104 with an Ultrascale+ ZU7.

My problem is that I want to use the included MIPI ip in Vivado. But those ip's are not compatible.

But they are compatible with ZU3EG, ZU6EG VU3P, KU9P etc

 

Anyone know why I cant use them with the ZU5?

 

best regards

Urban Wadelius

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florentw
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Registered: ‎11-09-2015

Hi @wadelius,

 

All 7-series except spartan-7 are currently supporting MIPI.

 

Only US+ has the HW for the D-PHY in the MIPI. For 7-series, you are expected you use an external PHY as per xapp894.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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florentw
Moderator
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Registered: ‎11-09-2015

Hi @wadelius,

 

But they are compatible with ZU3EG, ZU6EG VU3P, KU9P etc

Were did you find this information? As per PG232, I think MIPI is supported on all families starting with 7-series:

MIPI.JPG

 

Note: There are multiple IPs for MIPI:

  • MIPI DPHY
  • MIPI CSI2 RX Subsystem
  • MIPI CSI2 TX Subsystem
  • MIPI DSI TX

But it should be the same for every MIPI IP


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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wadelius
Participant
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2,347 Views
Registered: ‎05-04-2018

Hi Florent,

thanks for quick response.

 

This information was in the Vivado IP tool, but I saw that I use an old one version 2016.2, and maybe that's obsolete information in that version.

 

Does all 7-series support MIPI? I thought only the Ultrascale+ had the right hw to support mipi signal levels?

 

/Urban

 

 

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florentw
Moderator
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Registered: ‎11-09-2015

Hi @wadelius,

 

All 7-series except spartan-7 are currently supporting MIPI.

 

Only US+ has the HW for the D-PHY in the MIPI. For 7-series, you are expected you use an external PHY as per xapp894.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

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karnanl
Xilinx Employee
Xilinx Employee
2,248 Views
Registered: ‎03-30-2016

Hello @wadelius

 

@florentw is correct. But I want to add some new information regarding Spartan-7 support.


(D-PHY, CSI-2 TX/RX)

Spartan-7 supported from 2018.1

(DSI TX)

Spartan-7 supported from 2018.3

 

But I would recommended customer to use US+ device for MIPI since it can support D-PHY electrical spec natively.

 

Best regards

Leo


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daram123
Adventurer
Adventurer
2,095 Views
Registered: ‎01-19-2018

We Would appreciate your response.

clk_settle User param value in MIPI CSI-2 Tx IP

In MIPI DHPY {Product Guide 202} Default user parameters in 57 page tells only about HS_SETTLE {8:0 HS_SETTLE_NS R/W 135 + 10 UI} and the default value is 145 ns.
On the other hand, the clk_settle as explained in MIPI_D_PHY specification 548 page requires additional clk_settle param to be initiative. 

More information on Clk_settle param will be quite helpful. It's not given in MIPI CSI-2 Rx or Tx product guides.

Thanks.

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florentw
Moderator
Moderator
2,088 Views
Registered: ‎11-09-2015

Hi @daram123,

 

This is a different question and this topic was not created by you.

 

As per the guidelines for the video board:

4. Do not post a question on someone else's topic. Create a new topic if you have an issue. It might not be the same issue

I am closing this topic for new replies. Please create a new topic for your question.

 

Thank you for you understanding


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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