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egermann
Visitor
Visitor
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Registered: ‎03-21-2019

What is the depth of the Generic Short Packet FIFO in MIPI CSI-2 Receiver Subsystem?

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Hello,

on page 27, the MIPI CSI-2 Receiver Subsystem v4.0 LogiCORE IP Product Guide (pg232) states: Packets received with generic short packet codes are stored in a 31-deep internal FIFO [...]. I find this wording a bit confusing.

What exactly does 31-deep mean here? Is it bits? bytes? data words? How many Generic Short Packets can be stored in this FIFO?

I ran a simulation sending Generic Short Packets, and manually counted the packets in the waveform until the Short packet FIFO full flag in the Interrupt Status Register went high. However, this is very cumbersome and left me confused, since the flag went high after 47 generic short packets were received. This does not correspond in any way to the 31-deep stated in the IP Product Guide.

This led me to the assumption that this FIFO is not only for Generic Short Packets but for ALL kind of short packets? 

Best regards,
egermann

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karnanl
Xilinx Employee
Xilinx Employee
364 Views
Registered: ‎03-30-2016

Hello @egermann 

Thank you for letting me know that you don't have any issue using this register.
Anyway your understanding is correct that
-this FIFO is only for Generic Short packet.
-Since The register only 16bit wide so ECC data is not included.

If one-bit error occurs during data-transmittion , MIPI CSI-2 controller will fix the error-bit and store Generic short packet data into the FIFO.
If two-bits error occurs during data-transmittion , MIPI CSI-2 controller will discard the data,  it will not be pushed in the FIFO.

Thanks and regards
Leo


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karnanl
Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @egermann 

I understand your question. Let me confirm to internal team and get back to you.

BTW, did you see any issue using Generic Short packet register ?

Thanks & regards
Leo


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egermann
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Registered: ‎03-21-2019

Hello @karnanl 

Thank you for your reply. Long story short: everything works fine, I was just confused because of an error I produced myself by wrong configuration of the simulation, and because of the obscure wording in the Xilinx IP Product Guide. 

The Generic short packet register has worked fine for me. I have been able to read out the short packet FIFO without problems.

In my first post I stated that the Short packet FIFO full flag went high after 47 short packets - however, I found out this was because I did not configure everything correctly in my simulation.

Since my first post I also found out that the short packet FIFO is indeed only for generic short packets and does not store short packets that encode image information such as frame start, frame end, line start or line end.

I also found out that up to 32 generic short packets can be stored in the short packet FIFO. However, the 8 bits from ECC cannot be retrieved when reading out the FIFO - I assume they are not even stored.

karnanl
Xilinx Employee
Xilinx Employee
365 Views
Registered: ‎03-30-2016

Hello @egermann 

Thank you for letting me know that you don't have any issue using this register.
Anyway your understanding is correct that
-this FIFO is only for Generic Short packet.
-Since The register only 16bit wide so ECC data is not included.

If one-bit error occurs during data-transmittion , MIPI CSI-2 controller will fix the error-bit and store Generic short packet data into the FIFO.
If two-bits error occurs during data-transmittion , MIPI CSI-2 controller will discard the data,  it will not be pushed in the FIFO.

Thanks and regards
Leo


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karnanl
Xilinx Employee
Xilinx Employee
319 Views
Registered: ‎03-30-2016

Hello @egermann

If you feel that your question is answered. Could you please kindly mark this post as solved ?
So other forum users can learn from you.

Thanks & regards
Leo


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