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t-koyama
Visitor
Visitor
416 Views
Registered: ‎05-18-2018

What will be the lowest level FPGA for Displayport 8Gbps speed?

What will be the lowest level FPGA for Displayport 8.1Gbps speed?

I would like to know which device can be available Displayport 8.1Gbps.

PG230 has little information but it's not enough for us.

actually , we will use XCKU15P-1 but PG230 said Ultrascale + -1i,-1e limitation is 5.4 Gbps  .

I don't know why kintex ultrascale -1 grade cover 8.1Gpbs but kintex ultrascalePlus doesn't cover it.

Could you help us ?

 

 

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9 Replies
watari
Teacher
Teacher
387 Views
Registered: ‎06-16-2013

Hi @t-koyama 

 

Do you want to achieve HBR3 with the lowest level FPGA ?

Or, do you want to achieve ex. 8K with DSC with the lowest level FPGA ?

 

Best regards,

t-koyama
Visitor
Visitor
382 Views
Registered: ‎05-18-2018

Dear Watari

Thanks for your reply.

Actually we want to achieve HBR3 with the lowest level FPGA.

 

 

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t-koyama
Visitor
Visitor
378 Views
Registered: ‎05-18-2018

Dear watari

forgot one issue

we don't need DSC function , only need line rate.

 

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florentw
Moderator
Moderator
367 Views
Registered: ‎11-09-2015

HI @t-koyama 


I don't know why kintex ultrascale -1 grade cover 8.1Gpbs but kintex ultrascalePlus doesn't cover it.


Where did you find this information? This is from the latest PG300:

DP1.4.PNG

For both Ultrascale and Ultrascale+ you will need to use at least a -2 speedgrade if you want to support HBR3


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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t-koyama
Visitor
Visitor
339 Views
Registered: ‎05-18-2018

Dir Sir

Thank you for your answer

I've understood it. it solved.

This is not question only interesting.

but I have little confuse it ,because that data sheet update at August 31st and 

previous version described ,

it seems to be all Ultrascale + and Ultrascale cover 8.1Gbps,,,

Are there any problem on it ?

 

t-koyama_0-1599212329008.png

 

 

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florentw
Moderator
Moderator
333 Views
Registered: ‎11-09-2015

HI @t-koyama 

I believe this table was not mentioning the speedgrade, thus was not really following the Datasheet for the device.

The new version of the doc is clearer


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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florentw
Moderator
Moderator
214 Views
Registered: ‎11-09-2015

Hi @t-koyama 

Is everything clear for you on this subject?

Thanks


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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t-koyama
Visitor
Visitor
208 Views
Registered: ‎05-18-2018

Dear sir

Sorry for reply late.

I've got your meaning, and clear all things.

Thank you very much.

 

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aoifem
Moderator
Moderator
161 Views
Registered: ‎11-21-2018

Hi @t-koyama 

If this issue is resolved, could you mark the answer as 'accepted solution' so the community can find it faster? 

Aoife
Product Application Engineer - Xilinx Technical Support EMEA


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