cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
FallInTheFall
Visitor
Visitor
531 Views
Registered: ‎03-08-2021

When I send embedded non-image lines at the beginning of frame,there is no FS and FE in the frame.

Jump to solution

I want to send 1 lines F-EBD(datatype 0x12)+ 4 lines OB(datatype 0x37)+ 1876  lines RAW12(datatype 0x2c)+ 6 lines R-EBD(datatype 0x12)= 1887 lines using VC0 of MIPI CSI TX  IP. I set “Enable Register Based Frame End Generation”= true in GUI, and set XCsi2TxSs_SetLineCountForVC(&CsiTxSs,0,1887) . But there is no FS and FE on the oscilloscope .

When I set all the 1887 lines RAW12(datatype 0x2c), I can see FS before the first line and FE after the 1887 line on the oscilloscope. When I set all the 1887 lines EBD(datatype 0x12), there is no FS and FE on the oscilloscope.

So I wonder to know is there any other config for the MIPI TX in order to send frame structure like 1 lines F-EBD(datatype 0x12)+ 4 lines OB(datatype 0x37)+ 1876  lines RAW12(datatype 0x2c)+ 6 lines R-EBD(datatype 0x12 ? Thanks for your reply.

0 Kudos
1 Solution

Accepted Solutions
karnanl
Xilinx Employee
Xilinx Employee
428 Views
Registered: ‎03-30-2016

Hello @FallInTheFall 


INFO.png
Thanks for providing those information. Noted.

BTW, Does it mean Word Count is always 4320 for all lines ?
   a. DataType 0x12 : 2880pixel --> WC=4320 ? (Embedded Non-image 8bit)
   b. DataType 0x37 : 2880pixel --> WC=4320 ? (User Defined 8bit)
   c. Datatype 0x2c : 2880pixel --> WC=4320 (RAW12)
If this is the case WC setting for (a) and (b) lines is not correct. WC should be set as 2880 in (a) and (b) case.

>But I have two projects, difference of them is only datatype—— one is 0x2c, another is 0x12,
>so I wonder to know why 0x2c can make the FS and FE correct and 0x12 cannot.

0x2C is RAW12 (1 pixel is 12 bit)
0x12 is Embedded Non-Image (1 pixel is 8 bit)
So, WC setting should be set accordingly to match data byte number of each lines.

Kind regards
Leo


------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
Versal Example Designs : LINK
>>------------------------------------------------------------------------------------------------

View solution in original post

5 Replies
karnanl
Xilinx Employee
Xilinx Employee
508 Views
Registered: ‎03-30-2016

Hello @FallInTheFall 

Could you please share
1. Vivado version ?
2. Device model ?
3. Did you assert TUSER[0]=1 , on the first data byte of the first line ?
4. Could you please ensure that s_axis_tlast is triggered correctly on last pixel of every line ?
5. Could you please ensure that Word Count setting (TUSER[63:48]) is correct for every line ?
6. Do you have any ILA waveform to confirm (3)(4)(5) ?
7. Could you please check Interrupt Status Register (Offset - 0x024) , to ensure everything is working fine ?

Kind regards
Leo


------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
Versal Example Designs : LINK
>>------------------------------------------------------------------------------------------------
FallInTheFall
Visitor
Visitor
499 Views
Registered: ‎03-08-2021

Thanks!

1. Vivado version ?

——Vivado2020.1
2. Device model ?

——xczu5ev-sfvc784
3. Did you assert TUSER[0]=1 , on the first data byte of the first line ?

yes, I did.
4. Could you please ensure that s_axis_tlast is triggered correctly on last pixel of every line ?

yes, I ensure.
5. Could you please ensure that Word Count setting (TUSER[63:48]) is correct for every line ?

The Word Count is not change, always 2880pixel*12/8= 4320.
6. Do you have any ILA waveform to confirm (3)(4)(5) ?

I am not a good time to provide ILA waveform to confime (3)(4)(5). But I have two projects, difference of them is only  datatype—— one is 0x2c, another is 0x12, so I wonder to know why 0x2c can make the FS and FE correct and 0x12 cannot.


7. Could you please check Interrupt Status Register (Offset - 0x024) , to ensure everything is working fine ?

I will check the register. tks!

0 Kudos
karnanl
Xilinx Employee
Xilinx Employee
429 Views
Registered: ‎03-30-2016

Hello @FallInTheFall 


INFO.png
Thanks for providing those information. Noted.

BTW, Does it mean Word Count is always 4320 for all lines ?
   a. DataType 0x12 : 2880pixel --> WC=4320 ? (Embedded Non-image 8bit)
   b. DataType 0x37 : 2880pixel --> WC=4320 ? (User Defined 8bit)
   c. Datatype 0x2c : 2880pixel --> WC=4320 (RAW12)
If this is the case WC setting for (a) and (b) lines is not correct. WC should be set as 2880 in (a) and (b) case.

>But I have two projects, difference of them is only datatype—— one is 0x2c, another is 0x12,
>so I wonder to know why 0x2c can make the FS and FE correct and 0x12 cannot.

0x2C is RAW12 (1 pixel is 12 bit)
0x12 is Embedded Non-Image (1 pixel is 8 bit)
So, WC setting should be set accordingly to match data byte number of each lines.

Kind regards
Leo


------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
Versal Example Designs : LINK
>>------------------------------------------------------------------------------------------------

View solution in original post

FallInTheFall
Visitor
Visitor
355 Views
Registered: ‎03-08-2021

Yeah, when I changed word count to 1 lines F-EBD(datatype 0x12, WC=2880)+ 4 lines OB(datatype 0x37, WC=2880)+ 1876  lines RAW12(datatype 0x2c, WC=4320)+ 6 lines R-EBD(datatype 0x12, WC=2880)= 1887, FS and FE are both right.

Thanks karnanl for reminding me and resolving this issue.

karnanl
Xilinx Employee
Xilinx Employee
302 Views
Registered: ‎03-30-2016

Hello @FallInTheFall 

Thanks for the update.

Regards


------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
Versal Example Designs : LINK
>>------------------------------------------------------------------------------------------------
0 Kudos