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ackye
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Registered: ‎05-19-2020

When using Mipi core to receive 4k60 CMOS image, should it be connected to normal IO or high-speed IO? (GTH GTX GTP)

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When using Mipi core to receive 4k60 CMOS image, should it be connected to normal IO or high-speed IO? (GTH GTX GTP)

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karnanl
Xilinx Employee
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Registered: ‎03-30-2016

Hello @ackye 

> Can I connect 7 series FPGA and IMX274 through SUB-LVDS?

Yes you can. 7-series IO can support 576Mbps sub-lvds I/F,  no issue.
But, you will need to build your RX IP to receive data from IMX274.

Xilinx MIPI CSI-2 RX / MIPI D-PHY RX is designed to receive MIPI signals format only,
It will not work with Sub-LVDS I/F, the data format is different.

Thanks & regards
Leo

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karnanl
Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @ackye 

Answer : Normal IO.

BTW, what is your target device ?
I would like recommend to use UltraScale+ devices (UltraScale+ MPSoC or UltraScale+ Kintex) since these device has a native IO support for MIPI D-PHY and can support up to 2500Mbps line-rate usecase. You do not need any external device to receive MIPI signals from CMOS image sensors.

Please see also the following PGs for MIPI RX related docs.
   PG232 
   PG202

Hope this helps.

Regards
Leo

ackye
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Registered: ‎05-19-2020
Thank you, but because of size restrictions, I can only use ARTIX or KINTEX chips. CMOS is imx274
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ackye
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Registered: ‎05-19-2020

Thank you, but because of size restrictions, I can only use ARTIX or KINTEX chips. CMOS is imx274

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karnanl
Xilinx Employee
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Registered: ‎03-30-2016

Hello @ackye 

As mentioned in PG232, Xilinx has done interoperability test with IMX274 (using both UltraScale+ and 7-series devices).
See :
Clipboard09.png


Please note that using 4K@60fps format , IMX274 will send video signal using 4-lanes @1.44Gbps.
This usecase is tested using ZCU102 (UltraScale+ device).

For 7 Series, IP is tested and validated for max 1250 Mb/s (using external PHY, MC20901 from Meticom).
Perhaps line rates higher than 1250 Mb/s are selectable in the GUI, but we never tested line-rate above 1250Mbps in HW.

I would recommend using UltraScale+ device for your usecase.

>but because of size restrictions, I can only use ARTIX or KINTEX chips. CMOS is imx274

What is the meaning of "size restrictions" ? Is it a board size ? Could you please elaborate more ?

BTW, please see also XAPP894 for a concept implementing MIPI D-PHY compatible/compliance solution for 7-series devices.
7-series device cannot receive MIPI D-PHY signal without external PHY device, this will make your board size much larger.


Regards
Leo

ackye
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Registered: ‎05-19-2020

Can I connect 7 series FPGA and IMX274 through SUB-LVDS?   123.png

karnanl
Xilinx Employee
Xilinx Employee
367 Views
Registered: ‎03-30-2016

Hello @ackye 

> Can I connect 7 series FPGA and IMX274 through SUB-LVDS?

Yes you can. 7-series IO can support 576Mbps sub-lvds I/F,  no issue.
But, you will need to build your RX IP to receive data from IMX274.

Xilinx MIPI CSI-2 RX / MIPI D-PHY RX is designed to receive MIPI signals format only,
It will not work with Sub-LVDS I/F, the data format is different.

Thanks & regards
Leo

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ackye
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Registered: ‎05-19-2020

Thank you very much, by the way, can the artix-7 35t with 4 GPTs support HDMI2.O IP when outputting 4k 60hz video?

Is it necessary to connect the differential output signal to the high-speed IO port, when using 4k 60hz

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karnanl
Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello

 

>can the artix-7 35t with 4 GPTs support HDMI2.O IP when outputting 4k 60hz video?

 

This is a different topic. Please create a new thread/post to discuss this.

# But I do believe you already discussed on :

   https://forums.xilinx.com/t5/Video-and-Audio/When-HDMI-2-0-IP-core-outputs-4k-60hz-Must-use-high-speed-GPIO/td-p/1110556

# I think only HDMI 1.4 is supported with Artix GTP, as mentioned by PG235.

 

Regards
Leo