08-20-2020 07:13 PM
Why is the CLK differential line of hdmi2.0 TX connected to 1.8V HP instead of GTX / GTP
and Can I use GTX / GTP directly
08-22-2020 04:42 PM
I am not sure I understand your question.
Which clock are you referring to?
The reference clock for the GTs follows the requirements of the GT being used.
The TMDS clock is sent to a cable driver, this is explained in PG230, page 107.
If I have not answered your question, please clarify which clock/situation you are referring to.
08-23-2020 12:48 AM
Hdmi2.0 TX has four groups of differential lines（D0 D1 D2 CLK）. In the reference design zcu106 zcu102, d0-d2 is connected to the GTX port of FPGA, but the output CLK is connected to standard IO port（HP IO）. Can I also connect the CLK differential line output from GTX port
08-23-2020 02:49 PM
This is possible. See the PG230 sections on "Using Fourth GT Channel as TX TMDS Clock Source"
Using the 4th GT channel is actually recommended for noisy(high SI) designs as the GT channels have better SI characteristics as compared to standard IO.
There is an AR being edited for publishing that details how this is tested on a ZCU102 using the TED FMC. (AR# 72979 - available sometime soon)
Testing the 4th channel is possible as the TED FMC has a switch to enable the use of either clock from the FPGA.
09-02-2020 09:07 AM
I *believe* it can be connected directly as the SNDP159 will treat it the same as data lane. **This can be shown in the DP159's lane swapping capability.
However, please confirm using the SNDP159 datasheet as this is a SNDP159 requirement.