I am using the DDS Compiler v2.0 Coregen with ISE Evaluation 9.2i and IP Update 2. In my case the DDS Compiler generates a VHDL file with output widths 12:0, but the schematic symbol says 11:0. Other DDS configuration always gives the same problem: the VHDL entitity outputs are one bit wider each than the schematic instance outputs.
That's why the following two errors occur at the Synthesizer step:
ERROR:Xst:2587 - Port <cosine> of instance <dds> has different type in definition <dds_fix>. ERROR:Xst:2587 - Port <sine> of instance <dds> has different type in definition <dds_fix>.