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Rajan_G
Visitor
Visitor
615 Views
Registered: ‎01-31-2021

XAZU3EG – L1SFVA625I4586

Hi,

We have chosen XAZU3EG – L1SFVA625I4586 part for our project.

Does XAZU3EG – L1SFVA625I4586 part will support VESA DP V1.4 compatible?

Please suggest VESA DP V1.4 support part number, If not.

Thank you,

Rajan

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12 Replies
kshimizu
Xilinx Employee
Xilinx Employee
585 Views
Registered: ‎03-04-2018

Hello @Rajan_G ,

 

DP supports the VESA v1.2a on your FPGA device.  Please see the UG1085, p.923.

 

 

Best regards,

Kshimizu

 

Product Application Engineer Xilinx Technical Support

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Rajan_G
Visitor
Visitor
566 Views
Registered: ‎01-31-2021

HI, 

Thank you for your confirmation.

Could you please suggest VESA DP V1.4 support FPGA part number?

Also kindly share reference for eDP port interface (eDP to LVDS)

Is it required HD or HP ports in PL block for eDP port interface.

Please suggest.

Thank you 

Rajan

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florentw
Moderator
Moderator
515 Views
Registered: ‎11-09-2015

Hi @Rajan_G 

The  XAZU3EG – L1SFVA625I4586 part has a harden Displayport controller. This controller only support DP1.2.

In ZU+ devices you can implement the Displayport 1.4 IP in the Programmable Logic:

But this is using Gigabit tranceivers (not on HD or HP port) . The ZU3EG does not have any GT thus will not be able to support it. You need at least a ZU4EG device.

The eDP support is limited so fome specific features which are listed in the PG above. Please refer to it.

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Rajan_G
Visitor
Visitor
470 Views
Registered: ‎01-31-2021

Hi,

Thank you for your information.

Does XAZU3EG – L1SFVA625I4586 chip support MIPI DSI to eDP Interface?

Please suggest

Thank you 

Rajan

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florentw
Moderator
Moderator
458 Views
Registered: ‎11-09-2015

HI @Rajan_G 

There are few limitations I see with the XAZU3EG:

  • Xilinx does not have a MIPI DSI RX IP (only TX) -> thus you would need to create your own IP or find a 3rd party provider
  • the XAZU3EG does not have GTs thus you will need to use the harden Displayport controller which does not support eDP. You might need to check if there are external IC devices which can convert from DP to eDP. And this would be only DP1.2a (not DP1.4) and with only 2 lanes (so max 4k@30)

So you need to investigate with the above limitations. There is not really an answer I can give you which would be a clear yes or no


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Rajan_G
Visitor
Visitor
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Registered: ‎01-31-2021

Hi,

we are going to use serializer for Display port to FPD-Link IV interface.

In 'XAZU3EG – L1SFVA625I4586' Datasheet allocated only "DisplayPort Aux interface signals" in PS block. Remaining signals (D0±, D1±, D2±, D3±) not mentioned/allocated.

Is there required specific pins for D0±, D1±, D2±, D3± signals ?

Please suggest, If required.

Thank you

Rajan

Can we use any 

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florentw
Moderator
Moderator
414 Views
Registered: ‎11-09-2015

Hi @Rajan_G 

The data lanes are mapped to the PS GTR. Please refer to the Zynq Ultrascale+ TRM:
https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Rajan_G
Visitor
Visitor
286 Views
Registered: ‎01-31-2021

Hi,

My Serializer have Four Port Data lanes (D0±, D1±, D2± and D3±) for interface to PS block Display port. But in the Vivado tool we could not see 4 lane.

How to configure four data lanes in DP, Please provide your suggestion.

Thank you,

Rajan

 

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florentw
Moderator
Moderator
278 Views
Registered: ‎11-09-2015

Hi @Rajan_G 

Again, on the ZU3EG, there is not GT in the PL so it is not possible to implement the Displayport IP.

And the harden controller has only 2 lanes and using the PS GTR.

So it is not possible to configure 4 lanes in the ZU3EG device. 

This was already answered previously...


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Rajan_G
Visitor
Visitor
222 Views
Registered: ‎01-31-2021

Hi,

Thank you for continuous support,

Could you please suggest 4 lanes support parts? I think ZU4EG also will not support 4 lanes.

Also let me know, which one is preferable for interface the HDMI to PL block, HDMI to LVDS or HDMI to Parallel interface?

Thank you,

Rajan

Rajan

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florentw
Moderator
Moderator
218 Views
Registered: ‎11-09-2015

HI @Rajan_G 

If you use ZU4EG, then this device includes GTHs in the PL. Thus you can implement the Displayport 1.4 IP (see PG299). (but the harden controller still have only 2 lanes and support only DP1.2)

The same part can implement the HDMI 1/4/2.0 HDMI IP (see PG236)


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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florentw
Moderator
Moderator
216 Views
Registered: ‎11-09-2015

Hi @Rajan_G 

This discussion about the part selection is a discussion you should have with your FAE or Authorized Distributor. They should be able to point you to the right part to match your needs


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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