01-31-2021 06:58 PM
We have chosen XAZU3EG – L1SFVA625I4586 part for our project.
Does XAZU3EG – L1SFVA625I4586 part will support VESA DP V1.4 compatible?
Please suggest VESA DP V1.4 support part number, If not.
01-31-2021 09:54 PM - edited 01-31-2021 09:55 PM
Hello @Rajan_G ,
DP supports the VESA v1.2a on your FPGA device. Please see the UG1085, p.923.
Product Application Engineer Xilinx Technical Support
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01-31-2021 10:56 PM
Thank you for your confirmation.
Could you please suggest VESA DP V1.4 support FPGA part number?
Also kindly share reference for eDP port interface (eDP to LVDS)
Is it required HD or HP ports in PL block for eDP port interface.
02-01-2021 09:01 AM
The XAZU3EG – L1SFVA625I4586 part has a harden Displayport controller. This controller only support DP1.2.
In ZU+ devices you can implement the Displayport 1.4 IP in the Programmable Logic:
But this is using Gigabit tranceivers (not on HD or HP port) . The ZU3EG does not have any GT thus will not be able to support it. You need at least a ZU4EG device.
The eDP support is limited so fome specific features which are listed in the PG above. Please refer to it.
02-02-2021 06:25 AM
There are few limitations I see with the XAZU3EG:
So you need to investigate with the above limitations. There is not really an answer I can give you which would be a clear yes or no
02-02-2021 11:39 PM
we are going to use serializer for Display port to FPD-Link IV interface.
In 'XAZU3EG – L1SFVA625I4586' Datasheet allocated only "DisplayPort Aux interface signals" in PS block. Remaining signals (D0±, D1±, D2±, D3±) not mentioned/allocated.
Is there required specific pins for D0±, D1±, D2±, D3± signals ?
Please suggest, If required.
Can we use any
02-03-2021 12:48 AM
The data lanes are mapped to the PS GTR. Please refer to the Zynq Ultrascale+ TRM:
02-08-2021 10:44 PM
My Serializer have Four Port Data lanes (D0±, D1±, D2± and D3±) for interface to PS block Display port. But in the Vivado tool we could not see 4 lane.
How to configure four data lanes in DP, Please provide your suggestion.
02-09-2021 01:02 AM
Again, on the ZU3EG, there is not GT in the PL so it is not possible to implement the Displayport IP.
And the harden controller has only 2 lanes and using the PS GTR.
So it is not possible to configure 4 lanes in the ZU3EG device.
This was already answered previously...
02-10-2021 08:53 AM
Thank you for continuous support,
Could you please suggest 4 lanes support parts? I think ZU4EG also will not support 4 lanes.
Also let me know, which one is preferable for interface the HDMI to PL block, HDMI to LVDS or HDMI to Parallel interface?
02-10-2021 09:04 AM
If you use ZU4EG, then this device includes GTHs in the PL. Thus you can implement the Displayport 1.4 IP (see PG299). (but the harden controller still have only 2 lanes and support only DP1.2)
The same part can implement the HDMI 1/4/2.0 HDMI IP (see PG236)
02-10-2021 09:05 AM
This discussion about the part selection is a discussion you should have with your FAE or Authorized Distributor. They should be able to point you to the right part to match your needs