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Registered: ‎03-03-2017

XHdcp_KeyManagerInit function failing when running in debug mode

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Hi,

   I am working verifying HDCP 2.2 / 1.4 on the KC-705 example design in Vivado/SDK 2018.1 with the example design generated from 2018.1 and the application generated from the HDMI_TX_SS->Microblaze TX only project.

   I have successfully gotten both 2.2 and 1.4 keys programmed and verified reading and working on hardware and a monitor.

   I am now wanting to step through the code to understand how things work so I can port the application over to another set of custom hardware and I am finding the keys read successfully, but the XHdcp_KeyManagerInit function is failing when running in debug mode in the main() function in xhdmi_example.c.

   Within that function, both of the boxed red lines of code shown below are being hit.

hdcp7.png

 

   Does anybody know why it would work when I run without debug mode (i.e. in SDK click the Program FPGA button, and tell it to load the FPGA with the compiled/linked ELF file), but fails when I step through the code?   I guess I am also not sure what exactly this function is doing.

 

Thanks.

Tim

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

@tim_severance

 

It has been pointed out in PG224 that :

IMPORTANT: It is important to note that the LogiCORE HDCP IP does not include KMB. You will need

 

to use your own Key Management block and integrate it into your HDCP design as shown in Figure 3-1.

You should also refer to the Developing Tamper Resistant Designs with Xilinx Virtex-6 and 7 Series

 

--------------------

The reset in register is only used to reset HDCP IP, not KMB, but the issue seems to be related to Key management block, so it won't work

 

 

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Registered: ‎03-03-2017

It appears that the Xil_Out32 calls are not writing the data to BRAM memory.   I verified stepping through the code where I added a Xil_In32 right after the Xil_Out32 and all the "in"s were reading zeros even when the "out"s were writing non zero data.

Is this some kind of bug in SDK?   It is very strange that when I run in non-debug mode it works.

 

Thanks.

Tim

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Registered: ‎03-03-2017

I verified it is not a Xil_Out32/Xil_In32 issue since I wrote/read with the address being within the data region of the BRAM setup for Microblaze and it always read back what was written.

 

So it is an issue with the hdcp_keymngmt_blk not accepting the Xil_In32 for some reason.

 

Tim

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Registered: ‎03-03-2017

I verified the same problem occurs on Vivado/SDK 2018.2.   When I run in debug mode (i.e. right click application, Run-As -> Launch On Hardware system debugger or Debug-As -> Launch On Hardware system debugger) I get the terminal output below:

 

--------------------------------------
---  HDMI SS + VPhy Example v3.1   ---
---  (c) 2018 by Xilinx, Inc.      ---
--------------------------------------
Build Jun 21 2018 - 12:46:04
--------------------------------------
Before the HDCP functionality can be enabled,
the application will load the encrypted HDCP keys
from the HDMI FMC EEPROM.
The HDCP keys are protected with a unique password.
Please enter your password.
Enter Password ->.......
Password is valid.
Loading HDCP keys from EEPROM... done
Enabling HDCP functionality
HDCP 1.4 TX Key Manager Initialization error

Whereas when I run by loading the download.bit into the FPGA I get:

 

--------------------------------------
---  HDMI SS + VPhy Example v3.1   ---
---  (c) 2018 by Xilinx, Inc.      ---
--------------------------------------
Build Jun 21 2018 - 12:46:04
--------------------------------------
Before the HDCP functionality can be enabled,
the application will load the encrypted HDCP keys
from the HDMI FMC EEPROM.
The HDCP keys are protected with a unique password.
Please enter your password.
Enter Password ->.......
Password is valid.
Loading HDCP keys from EEPROM... done
Enabling HDCP functionality
---------------------------------

---------------------
---   MAIN MENU   ---
---------------------
i - Info
       => Shows information about the HDMI RX stream, HDMI TX stream,
          GT transceivers and PLL settings.
c - Colorbar
       => Displays the colorbar on the source output.
r - Resolution
       => Change the video resolution of the colorbar.
f - Frame rate
       => Change the frame rate of the colorbar.
d - Color depth
       => Change the color depth of the colorbar.
s - Color space
       => Change the color space of the colorbar.
l - GT PLL layout
       => Select GT transceiver PLL layout.
z - GT & HDMI TX/RX log
       => Shows log information for GT & HDMI TX/RX.
e - Edid
       => Display and set edid.
a - Audio
       => Audio options.
v - Video
       => Video pattern options.
m - Set HDMI Mode
n - Set DVI Mode
h - HDCP
       => Goto HDCP menu.


Starting colorbar
TX stream is up
--------
Colorbar :
        Color Format:     RGB
        Color Depth:      8
        Pixels Per Clock: 2
        Mode:             Progressive
        Frame Rate:       60Hz
        Resolution:       1920x1080@60Hz
        Pixel Clock:      148500000
--------

 

Tim

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Registered: ‎03-03-2017

I am thinking it has something to do with the fact that even when the RESET bit is set to 1 in the Key Management block (see pg224-hdcp.pdf page 14) the block can not be setup a second time I noticed.  Once it has been setup once, there is no way to run the setup again.

Is this a bug in the drive/IP?   I would think that if the reset bit is set high, then you can rerun the KeyManager setup function.

hdcp8.png

 

Tim

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Registered: ‎03-03-2017

Can somebody at Xilinx please confirm that the KeyManager IP block can be reset through AXI register writes and have the keys reporogrammed?   Also, can you please confirm that you can step through the function in debug mode?   Without this feature it makes it difficult to debug SDK code when I have HDCP enabled.

Tim

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

@tim_severance

 

If I remember correctly, I normally get "HDCP 1.4 TX Key Manager Initialization error" if I debug it without re-programming FPGA or reset Microblaze.

 

You can select reset option in Debug Configuration, select "reset entire system", and then it should work.

 

If it doesn't help, can you let me know the board type, and attach xci file, I will try to reproduce the problem with example design?

debug.JPG

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Registered: ‎03-03-2017

@xud,

   This worked, thank you very much.  It allowed me to run in debug mode.

   Any chance you can tell me why when you set the reset bit in the block that it does not actually reset the block to allow it to be setup again?   I would have thought that it would do a full reset on the block allowing me to set it up again.

Thanks.

Tim

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

@tim_severance

 

It has been pointed out in PG224 that :

IMPORTANT: It is important to note that the LogiCORE HDCP IP does not include KMB. You will need

 

to use your own Key Management block and integrate it into your HDCP design as shown in Figure 3-1.

You should also refer to the Developing Tamper Resistant Designs with Xilinx Virtex-6 and 7 Series

 

--------------------

The reset in register is only used to reset HDCP IP, not KMB, but the issue seems to be related to Key management block, so it won't work

 

 

View solution in original post

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Xilinx Employee
Xilinx Employee
1,958 Views
Registered: ‎08-01-2007

One additional thing I'd like to add on this.  The reason that this fails in Debug mode is that our example Key Manager hardware block actually has a lockout mechanism.  It only allows for the keys to be read one time.  Any additional reads result in a failure.  That is why you need to reset the hardware in Debug mode.  The idea is to try and minimize the possibility of an attack where the keys could be siphoned off by continuously reading form the keys from the EEPROM.

Chris
Versal ACAP: AI Engines | Embedded SW Support

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Registered: ‎03-03-2017

@chrisar,

   Thank you for that information, it is useful.

   I in fact updated the read function to check if it was already read, and it it was then it returns from the function as a success to allow the main application to continue.

   I had to do this since my application uses Microblaze resets often.

Tim

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2007

@tim_severance, as @xud pointed out, the HDCP block doesn't include the Key Manager.  The one included in the example design is just a reference block and the RTL is in clear text.  It is possible to modify the RTL code for the Key Manager block to remove this restriction or make other modifications for your particular application.

Chris
Versal ACAP: AI Engines | Embedded SW Support

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Registered: ‎03-03-2017

Good point.   Thank you.

Tim

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