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Contributor
Contributor
588 Views
Registered: ‎05-10-2019

Xilinx MIPI CSI-2 RX IP False path

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Hi,

 

I am using Xilinx Version 4 CSI-2 RX Subsystem IP block.

There are two subysystem clocks video_aclk and dphy_clk_200M 

My question is 

In general, Can i set false path between these clocks. ?

I am getting timing violation. It seems like a false path as it goes to a sync flop

Timing violation mipi csi2 rx block cl_stopstate_reg to sync_stages_ff_reg

This is path between dphy_clk_200M and video_aclk

Thanks

 

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Xilinx Employee
Xilinx Employee
511 Views
Registered: ‎03-07-2018

Re: Xilinx MIPI CSI-2 RX IP False path

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Hello @bhanu27 

Thank you for pointing out this issue with Xilinx MIPI CSI-2 RX IP. 

Slack (VIOLATED) :        -0.035ns  (required time - arrival time)
  Source:                 csi2RxSystem_i/mipi_csi2_rx_subsyst_0/inst/phy/inst/inst/bd_eee8_phy_0_rx_support_i/slave_rx.dphy_rx_fab_top/gen_csi_rx_clk_lane.dphy_rx_clk_lane/cl_stopstate_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_1  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            csi2RxSystem_i/mipi_csi2_rx_subsyst_0/inst/rx/inst/isr_cdc/PPI_CL_ASYNC[1].xpm_single_cl_sb/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@3.333ns period=6.666ns})

This issue is with CRC connectivity and can be ignored. 

Yes, you can add additional false_path constraint to work around this issue. 

I have reported this issue and it will get fixed next revision of this IP.

Regards,
Bhushan

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4 Replies
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Xilinx Employee
Xilinx Employee
563 Views
Registered: ‎03-07-2018

Re: Xilinx MIPI CSI-2 RX IP False path

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Hello @bhanu27 

Can you please share error details, log and Vivado version?

Regards,
Bhushan

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Contributor
Contributor
546 Views
Registered: ‎05-10-2019

Re: Xilinx MIPI CSI-2 RX IP False path

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Hi,

I am using version 4.0 of the CSI-2 RX IP.

Vivado version is 2018.3

Could you please confirm with IP designer that paths between following clocks 

in csi2-rx  dphy_clk_200M and video_aclk can be considered as false path

 

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Contributor
Contributor
537 Views
Registered: ‎05-10-2019

Re: Xilinx MIPI CSI-2 RX IP False path

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Hi Bhushan,

I am using vivado 2018.3

CSI2 IP version is 4.0

I have attached the timing report. As you can see the timing violations are for sync flops (Ist stage)

I was wondering in general if dphy_clk200 and video clk are asynchronous

 

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Xilinx Employee
Xilinx Employee
512 Views
Registered: ‎03-07-2018

Re: Xilinx MIPI CSI-2 RX IP False path

Jump to solution

Hello @bhanu27 

Thank you for pointing out this issue with Xilinx MIPI CSI-2 RX IP. 

Slack (VIOLATED) :        -0.035ns  (required time - arrival time)
  Source:                 csi2RxSystem_i/mipi_csi2_rx_subsyst_0/inst/phy/inst/inst/bd_eee8_phy_0_rx_support_i/slave_rx.dphy_rx_fab_top/gen_csi_rx_clk_lane.dphy_rx_clk_lane/cl_stopstate_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_1  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            csi2RxSystem_i/mipi_csi2_rx_subsyst_0/inst/rx/inst/isr_cdc/PPI_CL_ASYNC[1].xpm_single_cl_sb/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@3.333ns period=6.666ns})

This issue is with CRC connectivity and can be ignored. 

Yes, you can add additional false_path constraint to work around this issue. 

I have reported this issue and it will get fixed next revision of this IP.

Regards,
Bhushan

-------------------------------------------------------------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
-------------------------------------------------------------------------------------------------------------------------------------------------

View solution in original post