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wgabor
Contributor
Contributor
613 Views
Registered: ‎01-22-2019

Xilinx MIPI CSI2 RX subsystem IP 4.1 SOF is asserted at the third pixel besides the first of the frame.

Similar to https://forums.xilinx.com/t5/Video/MIPI-CSI-RX-Subsystem-SOF-stays-asserted-for-two-beats/m-p/1047754#M29056

In  https://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf we see the following

Start of Frame Signal 
The start of frame (SOF) signal is physically transmitted over the AXI4-Stream TUSER0 signal, and signifies the first pixel of a video field or frame. The SOF pulse is one valid transaction wide, and must coincide with the first pixel of the field or frame. SOF functions as a frame synchronization signal, allowing downstream cores to reinitialize, and detect the first pixel of a field or frame.
 
In a simulation (or Logic analyzer) waveform we see:
mipi_wave.jpg
 
Configuration:
mipi_config.png
 
It can also be reproduced by simulating the MIPI CSI2 TX subsystem example design, and adding the TUSER signal to the waveform.
mipi_config.png
4 Replies
karnanl
Xilinx Employee
Xilinx Employee
535 Views
Registered: ‎03-30-2016

Hello @wgabor 

I will confirm and give you feedback on this thread.

 

Thanks and regards
Leo


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karnanl
Xilinx Employee
Xilinx Employee
507 Views
Registered: ‎03-30-2016

Hello @wgabor 

It seems your report is correct. I can also reproduce the issue using MIPI CSI-2 TX simulation.
It seems that in some MIPI CSI-2 RX Subsystem configuration TUSER and TLAST can be asserted for multiple beat.
I will update this thread mid of next week.


Regards
Leo


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karnanl
Xilinx Employee
Xilinx Employee
461 Views
Registered: ‎03-30-2016

Hello @wgabor 

Patch solution for this issue is provided in
   AR#73100
   AR#73099
( ARs will be published early next week )

Could you please try this patch ?
Please note that after aplying the patch to Vivado you need to remove the pre-compiled library option in vivado.

Project Manager-> settings->IP-> unselect “Use Precompiled IP Simulation Libraries” -> rerun simulation


Alternative option is to add TCL command as follow

set_property sim.use_ip_compiled_libs 0 [current_project]

 


Thanks & regards
Leo


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karnanl
Xilinx Employee
Xilinx Employee
343 Views
Registered: ‎03-30-2016

Hello @wgabor

Do you have any updates on it ? Did you try to apply the patch to 2019.1 ?
https://www.xilinx.com/support/answers/73100.html


Thanks & regards
Leo


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