Xilinx MIPI D-Phy - Differences between Shared logic in Core/ Example Design

[gmoore]

Hi,This question relates to the MIPI D-PHY V 4.0 IP. 

My understanding, is that if one uses a core generated with 'Include Shared Logic in Core', that the line rate is fixed ? The line rate is specified in the 'Core Configuration' tab, and the internal PLL/MMCM use the input 200mhz core_clk to generate the required byte_clk, and the line clk. Thus, for a DPHY created with 'Shared Logic in Core', there may only ever be one line rate from that core. Is this correct ? 

My second question, is whether the 'Include Shared Logic in Example Design' allows a variable line rate. The user must still specify the line rate in the 'Core Configuration' tab, yet the inputs that actually determine the line rate for a mipi phy (txbyteclkhs_in,clkoutphy_in) are user-controlled. This suggests that, as long as the byteclk and the clkoutphy are in the correct ratio (1:8) that the line rate is controllable by the user ? Is this assumption correct ? If this assumption is correct, to what degree does specifying the line rate in the GUI matter ? 

Thanks in advance 

[nathanx · Accepted solution]

The unsupported feature section in the MIPI D-PHY Product Guide points out that "dynamic line rate change" is unsupported.

So the answer to your question is that shared logic in the core or in the example design does not affect if dynamic line rate is supported or not.