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Visitor
Visitor
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Registered: ‎10-03-2017

Xilinx Multi-scaler IP over Zynq7000

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I am trying to test Xilinx Multi-scaler IP over Zynq 7030. I based the block design on the Multi-scaler IP Example. I sucesfully generate the bitstream / XSA but when we try to build the BSP I get an error because my BSP do not have Video Common Library (xv_multi_scaler_l2.c:42:10: fatal error: xvidc.h: No such file or directory).

I test it with 2018.3 and Vitis 2019.2 and I get the same error.

In the Multi-Scaler IP documentation say that support Zynq 7000 and Ultrascale+. How I could include Video Common library to my BSP?

Best regards

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Moderator
Moderator
227 Views
Registered: ‎11-09-2015

Hi @calcius 

I believe I know what is the issue.

Can you try to add the following line to the file <Xilinx_installation_folder>Vitis\2019.2\data\embeddedsw\XilinxProcessorIPLib\drivers\v_multi_scaler_v1_0\data\v_multi_scaler.mdd

OPTION DEPENDS = (video_common);

I am trying to reproduce on my side. If this is the issue, it should affect any 7-series project and any KU/KU+/VU/VU+. 

I think this is working fine on the ZU+ devices because the DP controller driver will call the video_common driver. This is why this issue is not happening on the example design

Hope that helps


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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Moderator
Moderator
228 Views
Registered: ‎11-09-2015

Hi @calcius 

I believe I know what is the issue.

Can you try to add the following line to the file <Xilinx_installation_folder>Vitis\2019.2\data\embeddedsw\XilinxProcessorIPLib\drivers\v_multi_scaler_v1_0\data\v_multi_scaler.mdd

OPTION DEPENDS = (video_common);

I am trying to reproduce on my side. If this is the issue, it should affect any 7-series project and any KU/KU+/VU/VU+. 

I think this is working fine on the ZU+ devices because the DP controller driver will call the video_common driver. This is why this issue is not happening on the example design

Hope that helps


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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Moderator
Moderator
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Registered: ‎11-09-2015

Hi @calcius 

I was able to reproduce the issue. I confirmed that the workaround I gave is working.

I have reported the issue to the development team to get a fix for 2020.2

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Highlighted
Visitor
Visitor
68 Views
Registered: ‎10-03-2017

Thanks @florentw ,

I was out the office last days. I try it now and it build fine with 2019.2 and 2018.3

Best regards