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Registered: ‎03-30-2017

Z7015: timing violation using MIPI CSI-2 RX IP

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Hi there,

I'm using the MIPI CSI-2 RX IP in my design with Zynq7015.

I fed the dphy_clk_200M input of the IP with a 200MHz clock generated directly from the ZYNQ processor.

After implementation design, I get the following timing violations (internal to the MIPI CSI-2 IP) in figures below.

 

How to fix the violation, which seems to be internal to the core? I have already try with a different 200MHz clock, but without success,

 

Thanks in advance for any help.

 

Paolo.

 

 

Cattura.PNG
Cattura2.PNG
1 Solution

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Xilinx Employee
Xilinx Employee
703 Views
Registered: ‎03-30-2016

Hello @paolofalconearesys

 

1. Are you using 7-series device with slower speed grade ? (ex. -1, -2)

2. We are aware that HS_SETTLE register path has a big logic level that may be hard to close timing for some FPGA design. We already made some improvement on this and new IP is scheduled for 2018.3

3. For now, please set this path as a multi-cycle path to ease the timing.

    set_multicycle_path 2 -from <> -to  <>.

 

Thanks & regards

Leo

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Xilinx Employee
Xilinx Employee
704 Views
Registered: ‎03-30-2016

Hello @paolofalconearesys

 

1. Are you using 7-series device with slower speed grade ? (ex. -1, -2)

2. We are aware that HS_SETTLE register path has a big logic level that may be hard to close timing for some FPGA design. We already made some improvement on this and new IP is scheduled for 2018.3

3. For now, please set this path as a multi-cycle path to ease the timing.

    set_multicycle_path 2 -from <> -to  <>.

 

Thanks & regards

Leo

View solution in original post

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