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Visitor
Visitor
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Registered: ‎09-12-2018

ZCU102, MIPI CSI-2 RX subsystem problems on vivado 2017.3

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Hello. I am working on Zynq UltraScale+ ZCU102 Evaluation Board and Vivado HLx system suite version 2017.3.1. My goal is to transmit image datas to the DRAM of ZCU102 board from LI-IMX274-FMC image sensor. I was trying to make it with MIPI CSI-2 Receiver Subsystem v3.0. IP but I faced some problems described below.

 

- Board Automation

I was trying to connect the pins of the FMC_HPC0_connector (of the camera sensor) with the core chip of ZCU102 board on Vivado. Referring to 40 and 41 pages of the MPI CSI-2 Receiver v3.0 LogiCore IP Product Guide, there are some values other than 'custom' like 'fmc_hpc0_connector_EV_CSI2Rx_I2', which is the selection that automatically configures the MIPI CSI-2 Rx Subsystem to support IMX274 camera sensor which can be connected to EV FMC card as shown in Figure 1 below. It seemed to automatically connect the pins between MIPI IP and camera sensor if I understood right.

figure 1.png

<Figure 1>

 

But I just couldn't find 'Board tab' as shown in Figure 2 below.

 figure 2.png

<Figure 2>

 

I tried to force the value of 'CONFIG.DPHYRX_BOARD_INTERFACE' parameter into 'fmc_hpc0_connector_EV_CSI2Rx_l2' through block properties of MIPI IP, but it came with set_property error as below.

-------------------------------------------------------------------------------------------------------

ERROR: [BD 41-245] set_property error - Value 'fmc_hpc0_connector_EV_CSI2Rx_l2' is out of the range for parameter 'DPHYRX BOARD INTERFACE(DPHYRX_BOARD_INTERFACE)' for BD Cell 'mipi_csi2_rx_subsystem_0' . Valid values are – Custom.

-------------------------------------------------------------------------------------------------------

 

 

- Pin Assignment

Due to the above issues, I tried to do the Pin Assignment directly for connection of the core chip of the board to the FMC_HPC0_connector. However, two problems arose:

 

1) According to ‘MIPI CSI-2 Receiver Subsystem v3.0’ user guide’,

FMC_HPC0_connector(J5) is the pin to assign. However, referring to ‘LI-IMX274-FMC image sensor datasheet', FMC_HPC1_connector(J4) is the pin to assign. If J5 and J4 were same pin, it does not matter, however, the number of LA pairs seemed to be different with the one mentioned on ‘ZCU 102 Evaluation Board user guide’.

 

2) The pin assignment was still a challenge whether it is J4 or J5

If assign to FMC_HPC1_connector(J4),

According to ‘ZCU 102 Evaluation Board user guide’, The FMC_HPC1_connector(J4) is connected to 65 HP IO Bank. So, I selected  65 HP IO Bank and there were two location selection(AG10, AD10) to 'Data lane 3' as shown in Figure 3. But if I choose AG10 pin, it would connect with G18 pin on J4G, which seemed to be a useless pin referring to image sensor manual. So I selected AD10 pin and connected it to the H19 pin of the FMC_HPC1_connector(J4) as shown in Figure 4.

figure 3.png

<Figure 3> MIPI CSI-2 Rx Subsystem IP

 figure 4.png

<Figure 4> Reference - ‘ZCU 102 Evaluation Board’ user guide

 

 

However, as shown in Figure 5, the H20 pin in J4 is connected to the wrong place called DLO0P. In addition, all other selectable pins of other 'Data Lanes' (of MPI CSI-2 Rx subsystem IP) is associated with the wrong part according to the Image sensor datasheet.

Same issue was on J5.

figure 5.png

<figure 5> Reference - ‘LI-IMX274-FMC image sensor’ datasheet

 

What was I missing?

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Xilinx Employee
Xilinx Employee
2,297 Views
Registered: ‎03-30-2016

Hello @uuoo93

Let me comment on some of your questions.

 

0. Could you please use Vivado 2018.1.

    Highly suggest you to use MIPI IP generated from 2018.1 since we have some issue in our MIPI IP in 2017.3, especially with non-continuous clock mode.

    I can confirmed that Example Design is generated successfully using 2018.1.

 

1. Regarding the PG232 document

    Sorry for the confusion on PG232. "Board" tab is no longer selectable because "custom" is the only valid value as mentioned by your post. Please expect the PG232 document update around 2019.1 release.

 

2. I tried to generate MIPI CSI-2 RX Example Design (Vivado 2018.1),

    I can confirmed that our Example Design are using HP I/O bank 66 as default setting. So do you want to change this default pin assignment ? 

 

Thanks & regards

Leo

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XF_MIPI_EXAMPLE_D.png
5 Replies
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Xilinx Employee
Xilinx Employee
2,298 Views
Registered: ‎03-30-2016

Hello @uuoo93

Let me comment on some of your questions.

 

0. Could you please use Vivado 2018.1.

    Highly suggest you to use MIPI IP generated from 2018.1 since we have some issue in our MIPI IP in 2017.3, especially with non-continuous clock mode.

    I can confirmed that Example Design is generated successfully using 2018.1.

 

1. Regarding the PG232 document

    Sorry for the confusion on PG232. "Board" tab is no longer selectable because "custom" is the only valid value as mentioned by your post. Please expect the PG232 document update around 2019.1 release.

 

2. I tried to generate MIPI CSI-2 RX Example Design (Vivado 2018.1),

    I can confirmed that our Example Design are using HP I/O bank 66 as default setting. So do you want to change this default pin assignment ? 

 

Thanks & regards

Leo

View solution in original post

XF_MIPI_EXAMPLE_D.png
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Moderator
Moderator
2,147 Views
Registered: ‎11-09-2015

HI @uuoo93,

 

Did you get enough information from @karnanl's reply?

 

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Visitor
Visitor
2,004 Views
Registered: ‎09-12-2018

Hello karnanl.

Your advice helped me solve the pin assignment problem, but there’s one new problem which is generating MIPI Example Design.

 

Solved Problem

Problem 1. Reffering to your suggestion, I installed Vivado 2018.2. "Board” tab is selectable in Vivado 2018.2.

figure 5.png

Problem 2. Pin Assignment : This was my mistake. As I changed the clock lane, I could also change the data lane.

 

 

New Problem

I tried to generate MIPI CSI-2 RX Example Design (Vivado 2018.2), but failed. I generated Example design for the following process.

  1.  Create Project and set target board (Project Name : testestest)
    figure 0-0.png
  2.  Create Block Design and Add mipi_csi2_rx_subsystem IP
    figure 1.png
  3.  Open IP Example Design
    figure 2.png
  4.  Overwrite current project
    figure 2-1.png
  5.  Error Messages
    figure 3.png

    open_example_project -dir C:/Xilinx/project/testestest [get_ips design_1_mipi_csi2_rx_subsyst_0_0]

    ****** Vivado v2018.2 (64-bit)
    **** SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018
    **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

    source c:/Xilinx/project/testestest/.Xil/mipi_csi2_rx_subsystem_0/tmpEx.tcl
    # create_project -name tmp_mipi_csi2_rx_subsystem_0 -force
    # set_property part xczu9eg-ffvb1156-2-e [current_project]
    # set_property target_language verilog [current_project]
    # set_property simulator_language MIXED [current_project]
    # set_property coreContainer.enable false [current_project]
    # set_property board_part xilinx.com:zcu102_fmc_hpc0_connector_li-imx274mipi-fmc_fmc_connector:part0:3.2 [current_project]
    ERROR: [Board 49-71] The board_part definition was not found for xilinx.com:zcu102_fmc_hpc0_connector_li-imx274mipi-fmc_fmc_connector:part0:3.2. The project's board_part property was not set, but the project's part property was set to xczu9eg-ffvb1156-2-e. Valid board_part values can be retrieved with the 'get_board_parts' Tcl command. Check if board.repoPaths parameter is set and the board_part is installed from the tcl app store.
    INFO: [Common 17-206] Exiting Vivado at Fri Oct 19 11:52:34 2018...
    ERROR: [Common 17-69] Command failed: Unable to open example project; see previous messages.

  6.  Check current_board and current_board_part because of the previous messages
    figure 4.png

 

However, the set values are correct...

What was I missing..?? Do I have to use Vivado 2018.1..??

 

 

Thanks and regards.

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Xilinx Employee
Xilinx Employee
1,970 Views
Registered: ‎03-30-2016

Hello @uuoo93

1. I think your Example Design generation failed because you do not have the board file for "/proj/gsd/vivado/Vivado/2018.2"
    board name : zcu102_fmc_hpc0_connector_li-imx274mipi-fmc_fmc_connector:part0:3.2


2. Please check available board files in your local drive : {vivado}/2018.2/data/boards/board_files/****

3. It is strange because I cannot confirm the tab on my 2018.1/2018.2 on both Linux/Windows environment.
   Could you please select custom and re-generate your Example Design ?
   
4. I suggest you to use Linux environment, since windows limits path length to 260 characters.
    It might cause Example Design generation fail, If you are targeting a folder with a long character in Windows.

   

   BTW, I confirmed that MIPI Example design can ge generated successfully using Vivado 2018.2 (windows)
   if we can target folder hierarchy with a relatively short name.
 
5. 2018.2 should be okay



Thanks & regards
Leo

Highlighted
Visitor
Visitor
1,918 Views
Registered: ‎09-12-2018

Hello karnanl

I solved this problem!!

 

I confirmed board file, it was not the cause. Updated feature cause the problem.

 

 

Using below Updated feature(daughter card connections), Example Design generation failed.

figure 1.png

 

 

Not using below Updated feature(daughter card connections), Example Design generation succeeded.

figure 2.png

 

 

I think compatibility between MIPI IP and Vivado 2018.2 caused Example Design generation failed!

thanks and regards.

 

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