ZCU102 MIPI CSI2 RX Design Example: HDMI error when changing "Max bits per component" from 8 to 10

[andrewngo]

Hi all,

- I am using ZCU102 with Vivado 2177.4

- So far, I can bring CSI2 RX Design Example up and run without any problem

- Then I want to HDMI output at 10 bit per channel, so I go to HDMI IP and change Max bits per component from 8 to 10, modify to make sure VIDEO_IN connect to 64 bits input,  then Validate Design.

- I got error which indicate frequency between VPhys vid_phy_tx_axi4s_ch0 (which has frequency 148500000) and LINK_DATAX_OUT ( which change from 148500000 to 74250000)

- From Block Interface Properties, these "FREQ_HZ" fields from both above signal are gray out, so I can not modify to make them match.

- I have read some related issue from forum but they are not same as my case.

Please help.

Thanks

Andrew

[watari]

Hi @andrewngo

If you changed a color depth of video signal from 8bit to 10bit, you should change HDMI's clock frequency from orignal clock frequency to 1.25 multiplied value.

Could you try it, first ?

Best regards,

[andrewngo]

Hi @watari
Thanks,

Video input have changed its data width from 48 bits to 64 bits but clock should be same.

Hdmi ip use tmds clock from external si5324 for internal process but should allow me to modify the clock between hdmi ip and it’s phy from its GUI, but sadly no such settings from both sides

Thanks
Andrew

[andrewngo]

Hi all,

- If we click on txclkout block interface properties from VPHY, which is driver for link_clk, we will see either FREQ_HZ field empty or missing that may be the root cause.

- So I play around with VPHY GUI settings and somehow that field pop up right value clock, then I can synthesize the design example at 10bpp :), and it works!!

- Thank

Andrew

[watari]

Hi @andrewngo

Sorry for my late reply.

When you change color depth from 8bit to 10bit, you need to change clock frequency of link clock from 148.5MHz to 185.625MHz.

In this case, you should be change the setting on SI5324.

Would you make sure and try it ?

Best regards,

[andrewngo]

Hi @watari,

- Thanks for your quick reply.

- design example clock video data in at 300MHz with 2ppc, so it has enough bandwidth for 4k@30Hz.

- the clock I mentioned above is from VPHY IP to HDMI IP, and was generated by VPHY IP to HDMI during "validate design" process, so there is no way to adjust these clocks. The clock from SI5324 is also calculated and set up from standalone software, so it should be ok.

- however, as I mentioned above, after changing bpc from 8 to 10 bits, if I also launch VPHY IP settings, just don't change any thing then close it, at this time link_clock is set up correctly.

- Synthesize new setting success and I can see 4k@30Hz at 10 bpc

Thanks
Andrew
-

[florentw]

Hi @andrewngo,

I have tried and I am not able to reproduce your issue.

I have changed the HDMI from 8 to 10 bpc. The to simulate a 64-bit input I have used an AXI4-Stream subset converter.

I think you need to investigate the error you get. You are probably crossing 2 clock domains.

Regards,

[andrewngo]

Hi @florentw

You must generate project from HDMI TX only example for ZCU102, and start changing from 8 to 10 bpc, change test pattern generator to 10 bpc, then validate design.



Andrew

[florentw · Accepted solution]

Hi @andrewngo,

It should not change anything...

I have tried and I have the same behaviour, no error.

Please try again to regenerate the MIPI exdes and modify only the TPG and HDMI 8 to 10 bpc. Try to validate the bd twice in a row.

Regards,

[florentw]

Hi @andrewngo,

Do you have any updates on this?

If  everything clear for you on this subject, please kindly close the topic by marking one reply as accepted solution.

Thanks and Regards,

[andrewngo]

@florentw

- I tried to duplicate problem today by create new project of HDMI Example Design, and I got no problem to synthesize it :(.

- I still keep project that failed on this issue, but I may did something that cause it happen.

- I will close this isse

Thanks

Andrew

Thanks you your help