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peakpeak
Adventurer
Adventurer
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Registered: ‎03-31-2020

ZCU104 - hdmi_tx_ss tx-clk not ready

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Hi,

I am making the VCU TRD (originally designed for ZCU106) to work on ZCU104.

However, it seems I have problems with clocking (idt8t49n24x), which results in the below boot log: HDMI TX SS and VCU IP do not work:

 

[    7.289913] dp159 0-005e: probed
[    7.294689] dp159 0-005e: probe successful
[    7.317029] xilinx-vphy a0060000.vid_phy_controller: probed
[    7.323165] VPhy version : 02.02 (0000)
[    7.327260] xilinx-vphy a0060000.vid_phy_controller: probe successful
[    7.361295] xilinx-hdmi-rx a0000000.v_hdmi_rx_ss: probed
[    7.368938] xlnx-drm-hdmi a0020000.v_hdmi_tx_ss: probed
[    7.372114] xvphy_phy_init((____ptrval____)).
[    7.374222] xlnx-drm-hdmi a0020000.v_hdmi_tx_ss: hdmi tx audio disabled in DT
[    7.378572] xvphy_phy_init((____ptrval____)).
[    7.390125] xvphy_phy_init((____ptrval____)).
[    7.394774] xlnx-drm-hdmi a0020000.v_hdmi_tx_ss: tx-clk not ready -EPROBE_DEFER
[    7.429142] xilinx-hdmi-rx a0000000.v_hdmi_rx_ss: Using 2 EDID blocks (256 bytes) from 'xilinx/xilinx-hdmi-rx-edid.bin'.
[    7.440120] 
[    7.440120] Successfully loaded edid.
[    7.445444] xilinx-video amba_pl@0:vcap_hdmi: Entity type for entity a0000000.v_hdmi_rx_ss was not initialized!
[    7.456215] xilinx-hdmi-rx a0000000.v_hdmi_rx_ss: probe successful
[    7.463052] xlnx-drm-hdmi a0020000.v_hdmi_tx_ss: probed
[    7.468362] xlnx-drm-hdmi a0020000.v_hdmi_tx_ss: hdmi tx audio disabled in DT
[    7.475577] xlnx-drm-hdmi a0020000.v_hdmi_tx_ss: tx-clk not ready -EPROBE_DEFER
[    7.731490] xilinx-vcu xilinx-vcu: Could not get core_enc clock
[    7.746316] xlnx-drm-hdmi a0020000.v_hdmi_tx_ss: probed
[    7.751798] xlnx-drm-hdmi a0020000.v_hdmi_tx_ss: hdmi tx audio disabled in DT
[    7.758999] xlnx-drm-hdmi a0020000.v_hdmi_tx_ss: tx-clk not ready -EPROBE_DEFER
[    7.766615] VCU PLL: enable
[    7.770212] xilinx-vcu xilinx-vcu: xvcu_probe: Probed successfully
[    7.776855] xlnx-drm-hdmi a0020000.v_hdmi_tx_ss: probed
[    7.782148] xlnx-drm-hdmi a0020000.v_hdmi_tx_ss: hdmi tx audio disabled in DT
[    7.789380] xlnx-drm-hdmi a0020000.v_hdmi_tx_ss: tx-clk not ready -EPROBE_DEFER
[    7.880065] al5d a0120000.al5d: l2 prefetch size:10526720 (bits), l2 color bitdepth:8
[    7.889198] xlnx-drm-hdmi a0020000.v_hdmi_tx_ss: probed
[    7.894479] xlnx-drm-hdmi a0020000.v_hdmi_tx_ss: hdmi tx audio disabled in DT
[    7.901693] xlnx-drm-hdmi a0020000.v_hdmi_tx_ss: tx-clk not ready -EPROBE_DEFER
.......
Therefore, the linux boots with the following amba devices
root@xilinx-zcu104-2019_1:~# cd /sys/devices/platform/amba
root@xilinx-zcu104-2019_1:/sys/devices/platform/amba# ls
driver_override fd500000.dma ff020000.i2c ffa00000.perf-monitor ffae0000.dma
fd070000.memory-controller fd510000.dma ff030000.i2c ffa10000.perf-monitor ffaf0000.dma
fd0b0000.perf-monitor fd520000.dma ff070000.can ffa50000.ams modalias
fd0c0000.ahci fd530000.dma ff0a0000.gpio ffa60000.rtc of_node
fd400000.zynqmp_phy fd540000.dma ff0e0000.ethernet ffa80000.dma power
fd490000.perf-monitor fd550000.dma ff0f0000.spi ffa90000.dma subsystem
fd4a0000.zynqmp-display fd560000.dma ff150000.watchdog ffaa0000.dma uevent
fd4b0000.gpu fd570000.dma ff170000.mmc ffab0000.dma
fd4c0000.dma fd6e0000.cci ff960000.memory-controller ffac0000.dma
fd4d0000.watchdog ff000000.serial ff9d0000.usb0 ffad0000.dma

If I changed the idt8t49n24x to another 300MHz fixed clock, the "tx-clk not ready" error disappears, but gstreamer got problem with displaying the stream.

Below is my system-user.dtsi.

/ {	
	chosen {
		bootargs = "earlycon clk_ignore_unused consoleblank=0 cma=1557M uio_pdrv_genirq.of_id=generic-uio root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait ";
		stdout-path = "serial0:115200n8";
	};

};

&amba_pl {	
        vid_stream_clk: vid_stream_clk {
                compatible = "fixed-clock";
                #clock-cells = <0>;
                clock-frequency = <300000000>;
        };

        vid_s_axi_clk: vid_s_axi_clk {
                compatible = "fixed-clock";
                #clock-cells = <0>;
                clock-frequency = <99990000>;
        };
	hdmi_dru_clk: clock-generator-hdmi-dru-clk {
                        compatible = "fixed-clock";
                        #clock-cells = <0>;
                        clock-frequency = <156250000>;
                };
	misc_clk_0: misc_clk_0 {
			#clock-cells = <0>;			
			clock-frequency = <300000000>;
			compatible = "fixed-clock";
		};
	misc_clk_1: misc_clk_1 {
			#clock-cells = <0>;
			clock-frequency = <148500000>;
			compatible = "fixed-clock";
		};
	misc_clk_2: misc_clk_2 {
			#clock-cells = <0>;
			clock-frequency = <297000000>;
			compatible = "fixed-clock";
		};
	misc_clk_4: misc_clk_4 {
			#clock-cells = <0>;
			clock-frequency = <100000000>;
			compatible = "fixed-clock";	
	};
	refhdmi: refhdmi {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <40000000>;
	};
};

&mpsoc_ss_hdmi_ctrl_iic {	
			clocks = <&vid_s_axi_clk>;
			status = "okay";
			idt8t49n24x: clock-generator@6c {
			status = "okay";
			compatible = "idt,idt8t49n24x";
			#clock-cells = <1>;
			reg = <0x6c>;
			/* input clock(s); the XTAL is hard-wired on the ZCU104 board */
			clocks = <&refhdmi>;
			clock-names = "input-xtal";
			settings = [
				..../*copied from Revision platform */
				];
		};
	/* DP159 exposes a virtual CCF clock. Upon .set_rate(), it adapts its retiming/driving behaviour */
	dp159: hdmi-retimer@5e {
		status = "okay";
		compatible = "ti,dp159";
		reg = <0x5e>;
		#address-cells = <1>;
		#size-cells = <0>;
		#clock-cells = <0>;
	};

};


&vid_phy_controller {
        clock-names = "vid_phy_axi4lite_aclk", "dru-clk";
        clocks = <&vid_s_axi_clk>, <&hdmi_dru_clk>;
};

&tpg_port0 {
        xlnx,video-format = <0x3>;
};

&hdmi_input_v_hdmi_rx_ss_0 {
	clock-names = "s_axi_cpu_aclk", "s_axis_video_aclk";
	clocks = <&vid_s_axi_clk>, <&vid_stream_clk>;
};

&hdmi_input_v_proc_ss_0 {
	compatible = "xlnx,v-vpss-scaler";
};

&axi_intc_0 {
	interrupt-parent = <&gic>;
	interrupts = <0 108 4>;
};

&hdmi_output_v_hdmi_tx_ss_0 {	
	clock-names = "s_axi_cpu_aclk", "s_axis_video_aclk", "txref-clk", "retimer-clk";
	clocks = <&vid_s_axi_clk>, <&vid_stream_clk>, <&idt8t49n24x 2>, <&dp159>;	
};
&hdmi_output_v_mix_0 {
	/delete-property/ clock-names;
	clocks = <&idt8t49n24x 2>;
	xlnx,dma-addr-width = <64>;
};
&xx_mix_master {
        /delete-property/xlnx,layer-streaming;
        /delete-property/dma-names;
        /delete-property/dmas;
};

Could you please help me in this case?

It seems my problem is relating to this post, even I declared manually on system-user.dtsi (as like VCU TRD), but there was no luck.

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xud
Xilinx Employee
Xilinx Employee
770 Views
Registered: ‎08-02-2007

@peakpeak 

For ZCU104 board, you can refer to the device tree file from revision design : https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842370/reVISION+Getting+Started+Guide

it targets at ZCU104 board, using IDT clock generator

View solution in original post

2 Replies
peakpeak
Adventurer
Adventurer
831 Views
Registered: ‎03-31-2020

According to this

 DRM framework requests the registered clock producer (SI5324/SI5319 for Xilinx HDMI) to generate the clock for desired mode. Availability of this clock is checked by PHY using tx_refclk_rdy port pin. After this pin is asserted HIGH PHY’s internal state machine is triggered to lock onto the incoming frequency and stream transmission starts. As a last step the driver then configures the external LVDS to TMDS level shifter component (DP159), via CCF framework, which will convert the GT output signals to HDMI interface.

How can I check whether the idt8t49n24x is working or not? Is there any configurations to check if the clock is started yet and print on console?

0 Kudos
xud
Xilinx Employee
Xilinx Employee
771 Views
Registered: ‎08-02-2007

@peakpeak 

For ZCU104 board, you can refer to the device tree file from revision design : https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842370/reVISION+Getting+Started+Guide

it targets at ZCU104 board, using IDT clock generator

View solution in original post