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matt@opteran.com
Observer
Observer
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Registered: ‎12-05-2019

Zynq-7000 MIPI CSI-2 RX Subsystem IO selection & ordering

I am using the resistor network (compatible solution) of XAPP894 to connect a CSI-2 camera to a Zynq-7000 series SoC, using the MIPI CSI-2 RX Subsystem for interfacing in logic. This allows the connection of a four lane CSI-2 interface to ten differential pairs - 5 HS signals using LVDS_25, 5 LP signals using HSUL_12.

Question 1: PG202 states for 7 series FPGAs "Non-continuous IO usage is allowed for D-PHY TX and RX interfaces but not recommended.". Does signal ordering matter within a continuous block? I.e. could I use a (DATA2, DATA3, CLK, DATA0, DATA1) ordering, provided the block is contiguous? Similarly, does this continuity requirement encompass all ten HS and LP pairs, and is there a recommended ordering? For example should HS and LP signals be interleaved in the bank, or separated into two blocks? I also note that https://www.xilinx.com/products/boards-and-kits/1-d2cwd1.html does not use continuous IO.

Question 2: Are all five LP signals always required by the CSI-2 RX subsystem? Is this camera specific? I note the Trenz Zynqberry board only includes the LP signal for DATA0.

 

Thanks all

Matthew Watson

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karnanl
Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello matt@opteran.com 

A1. Non-continous IO usage is allowed.
      Please create a simple test design , to check your MIPI CSI-2 RX pin assignment validity with Vivado.
      Xilinx SP701 board implemented this resistor network for MIPI CSI-2 I/F. You might interested to check the board schematic.

A2. All LP signals are required.

 

>I am using the resistor network (compatible solution) of XAPP894 to connect a CSI-2 camera to a Zynq-7000 series SoC, using the MIPI CSI-2 RX Subsystem for interfacing in logic. 


It would be great if you can do board simulation before creating your board.
Please ensure to put all resistors near FPGA, do not implement those resistors on different board , especially if your are using a relatively high MIPI D-PHY line-rate.

Thanks & regards
Leo


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matt@opteran.com
Observer
Observer
385 Views
Registered: ‎12-05-2019

Thank you for your help Leo.

 

I have a couple more questions:

  • Why does xapp894 use 150ohm differential terminations when MIPI D-PHY is 100ohm?
  • Is it possible to use the Zynq's 100ohm internal differential termination instead?

 

Thanks again

Matt

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karnanl
Xilinx Employee
Xilinx Employee
370 Views
Registered: ‎03-30-2016

Hello Matt matt@opteran.com 

Your understanding is correct that MIPI D-PHY specifies that receiver's differential input impedance is 100ohm.
But, please note that 7-series devices do not have a native support for MIPI D-PHY.

XAPP894 proposed a method to receive MIPI D-PHY signal with 7-series IO.
The resistor network is "a compatible solution" since it will cover a typical MIPI D-PHY signal requirement.

Resistor network implemented on SP701 board is our recommendation.
We have never tested XAPP894 using IO 100ohm internal termination.  You need to do simulation and HW test on your own, to see if using IO internal termination, can receive MIPI D-PHY signal correctly.

Kind regards
Leo


------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
Versal Example Designs : LINK
>>------------------------------------------------------------------------------------------------