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Participant
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Registered: ‎06-19-2018

Zynq ultrascale+ SelectIO ZCU104 Evaluation kit

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In Zynq ultrascale+ SelectIO - MIPI CSI-2 RX PHY, If we using 2-lane mipi dphy interface in one nibble. Then, can we use the other nibble pins in that same byte group as GPIO? 

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Community Manager
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Registered: ‎08-08-2007

In general yes, if you use the CSi-2 RX PHY then the rest of the nibble can be used as GPIO. You would need to use an IOSTANDARD that is compatible with the MIPI IOSTANDARD. Table 1-77: VCCO and VREF Requirements for Each Supported I/O Standard of UG571 lists the Vcco and Vref requirements of each standard to help you understand which standard can be combined. Vivado pin placement also has these rules built in.

http://www.xilinx.com/support/documentation/user_guides/ug571-ultrascale-selectio.pdf

 

If you are using the ZCU104 board this has a specific pinout, there is a Master Constraints file and you need to stick to the IOSTANDARDs used here. See Appendix B of UG1267

http://www.xilinx.com/support/documentation/boards_and_kits/zcu104/ug1267-zcu104-eval-bd.pdf

Thanks,
Sandy

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Community Manager
Community Manager
1,423 Views
Registered: ‎08-08-2007

In general yes, if you use the CSi-2 RX PHY then the rest of the nibble can be used as GPIO. You would need to use an IOSTANDARD that is compatible with the MIPI IOSTANDARD. Table 1-77: VCCO and VREF Requirements for Each Supported I/O Standard of UG571 lists the Vcco and Vref requirements of each standard to help you understand which standard can be combined. Vivado pin placement also has these rules built in.

http://www.xilinx.com/support/documentation/user_guides/ug571-ultrascale-selectio.pdf

 

If you are using the ZCU104 board this has a specific pinout, there is a Master Constraints file and you need to stick to the IOSTANDARDs used here. See Appendix B of UG1267

http://www.xilinx.com/support/documentation/boards_and_kits/zcu104/ug1267-zcu104-eval-bd.pdf

Thanks,
Sandy

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