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yyzq
Visitor
Visitor
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Registered: ‎10-27-2008

a problem about xapp1248

We have designed a sdi module based on xapp1248. The module works well most of the time. But the RX logic may cann't decode the the input SDI signal some time after the board power on. It seems that  Initialization did not complete normally. Since the probability of this problem is very low, I have not yet obtained the working state of each state machine when abnormal. I will continue to experiment for more information.

My problem is why the RX/TX control state mochine desiged with a fail state ?  From the rlt code,I found that If the DRP verification fails, an error will be returned. But i want to know what may cause the DRP validation to fail?

 

thanks a lot!

 

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karnanl
Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @yyzq 

Could you please open the readme.txt and confirm if the XAPP version is 1.5 (latest version) ?
XAPP1248_version.png

Regards
Leo


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yyzq
Visitor
Visitor
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Registered: ‎10-27-2008

Yes, my base xapp is V1.5.

From the revision history : 04APR2018 1.5 Added Hot-Plug logic and controlled through EN_HOT_PLUG_LOGIC parameter (default is 0)

Should i enable the EN_HOT_PLUG_LOGIC  parameter,why v1.5 add this logic but unenalbed?

I also have some questions about the rx control state machine in kugth_uhdsdi_rx_control.v. The fsm will jump from PLL_WAIT_LOCK2_STATE to SETTLE_STATE when both plllock_m0 and plllock_m1 high. But I think it is more reasonable to wait until the gt_rx_reset_done_in signal is high. gtwiz_reset_all_in signal will trig the fsm in gtwiz_reset to reset the gt after power up. RX control fsm should wait the power up reset done before changing the gt configure.

 

 

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karnanl
Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @yyzq 

1. EN_HOT_PLUG_LOGIC is disabled in the XAPP1248 v1.5 to preserve the compatibility with previous XAPP version.
2. If you might reset XAPP1248 when sdi input signal is not ready/stable, or you might do cable plug/unplug test on your system,
Please enable EN_HOT_PLUG_LOGIC. (parameter EN_HOT_PLUG_LOGIC=1)
3. Pardon me, I cannot comment on the FSM modification proposal, since we would recommend users to use the XAPP1248 as is.

Regards
Leo


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If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
Versal Example Designs : LINK
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yyzq
Visitor
Visitor
295 Views
Registered: ‎10-27-2008

OK, thanks a lot for your relay. I will do more test to get more info about the wrong state.

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