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leoleonis
Observer
Observer
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Registered: ‎07-15-2019

are thee customer specific solutions

This is related to my DPHY asynchronous question, however in that tread was no reply possible, therefore a new one: 

I think, I got all Information I need, however, it leads me to another question:

If Infineon is asking for customer specific Version of the DPHY core, is this possible? As an Information -signal, if all Lanes started at the same high-speed clock edge, would be easy to create and to make it available on the PPI output. As the core is not source-open, I can not do it by myself.


on another forum place I posted the following question, with no answer until know, but as it is related to this one, I repeat it here:

minimal lines rate for high speed IO. 

I have a Design with Ulrascale+ MPSOC

in the high speed selectIO wizzard I find a minimal requirement for the linerate of 375Mbps. 
why is this that high?

 

I my Design I would need a range from 80Mbps up to 1000Mbps.

there is also the DPHY-Core; with this the minimal linerate is 80Mbps, which would be o.k.

I suppose, the DPHY-Core as well as the high speed selectIO wizzard are using the same ISERDES in FPGA HW?

So, if I configure the select IO-wizzard with 375Mbps, will it run, if the Input Line-rate is just 80Mbps?

thank you, Leo

 

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karnanl
Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @leoleonis 

>in the high speed selectIO wizzard I find a minimal requirement for the linerate of 375Mbps.
>why is this that high?

This is an IO spec as mentioned in datasheet.
Minimum PLL VCO freq is 750MHz, I believe this is limit your SelectIO usecase to 375Mbps.
UltraSCalep_PLL_SPEC.png

>So, if I configure the select IO-wizzard with 375Mbps, will it run, if the Input Line-rate is just 80Mbps?

No. It will not work.

>I suppose, the DPHY-Core as well as the high speed selectIO wizzard are using the same ISERDES in FPGA HW?

For line-rate below 600Mbps,
Xilinx D-PHY IP is using "over-sampling" method to overcome 375Mbps IO/PLL  limitation, so it can support MIPI D-PHY minimum line-rate requirement 80MBps.


Kind regards
Leo


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