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Contributor
Contributor
690 Views
Registered: ‎01-16-2019

aurora 8b 10b connect vdma question

i use aurora 8b ip ,i config this ip rx-simplex-timer mode, rx data is right, i connect user_m_axi_rx interface with axis data fifo(async), than i connect fifo m_axis interface to vdma s2mm interface, i use ila for debug s2mm, but the vdma can't move data to ddr,i don't kown why.

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Moderator
Moderator
661 Views
Registered: ‎11-09-2015

Hi @mountainfpga 

How did you configure the VDMA?

Did you check  the status register?

Does the data from Aurora include the video signals (tuser for SOF and tlast for EOL)?

I have wrote some examples using the VDMA as part of my video series. You might want to have a look to understand how the VDMA is working. Maybe start with a TPG as a source and then move the VDMA

Video Series 24: Using the AXI VDMA in Triple Buffer Mode

Video Series 25: Debugging issues on the AXI VDMA IP

Video Series 26: Examples of advanced uses of the AXI VDMA IP


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Contributor
Contributor
633 Views
Registered: ‎01-16-2019

because of my vdma config fsync option,I use aurora framming,which has no tuser,so vdma write is not work, thanks

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Moderator
Moderator
596 Views
Registered: ‎10-04-2017

Hi @mountainfpga,

 

I wanted to confirm that without tuser VDMA will not work as it uses tuser as control logic.

Do you have other questions on this topic or is it clear for you?

 

Thanks,

Sam

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Xilinx Video Design Hub
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Contributor
Contributor
577 Views
Registered: ‎01-16-2019

I have solved this problem.
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Moderator
Moderator
556 Views
Registered: ‎11-21-2018

Hi @mountainfpga 

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply).

 

Otherwise, would you be able to share your solution for other members? 

 

Regards, 

Aoife
Product Application Engineer - Xilinx Technical Support EMEA
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Contributor
Contributor
542 Views
Registered: ‎01-16-2019

ok,no problem, how to share it?
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Moderator
Moderator
476 Views
Registered: ‎11-21-2018

Hi @mountainfpga 

Can you describe what you did to solve this issue so other members of the community can replicate your solution if they need to?

Regards,

Aoife
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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