Showing results for 
Show  only  | Search instead for 
Did you mean: 
Registered: ‎11-29-2018

axi4s to videoout IP core underflow problem when using AXIVDMA as interlacer with VPSS as deinterlacer

Hello Community members,

I have implemented a design where I am interlacing a tpg generated 1080p (YCbCr 4:2:2) video with VDMA(Triple buffer). The interlaced video generated by vdma when directly passed on to axi4s_videoout IP core with VTC (1080i) gets the axi4s_videoout IP (independent clock mode, timing mode: slave, hysteresis level: 12) to lock.

However when I use VPSS(Deinterlaced mode Only) and try the axi4s_vidout IP block to generate 1080p native video for HDMI on zc702 eval board, the axi4s_vidout IP block doesnt get locked and the underflow flag is activated and there is no activity on video_out port.


the sysclk and videoout clock are same 150 MHz, 

Here is my vdma configuration:


/* Start of VDMA Configuration */
/* Configure the Write interface (S2MM)*/
// S2MM Control Register
Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x30, 0x8B);
//S2MM Start Address 1
Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0xAC, 0x10000000);
//S2MM Start Address 2
Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0xB0, 0x10600000);
//S2MM Start Address 3
Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0xB4, 0x10C00000);
//S2MM Frame delay / Stride register
Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0xA8, Width*2);
// S2MM HSIZE register
Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0xA4, Width*2);
// S2MM VSIZE register
Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0xA0, Height);

/* Configure the Read interface (MM2S)*/
// MM2S Control Register
Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x00, 0x8B);
// MM2S Start Address 1
Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x5C, 0x10000000);
// MM2S Start Address 2
Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x60, 0x10600000);
// MM2S Start Address 3
Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x64, 0x10C00000);
// MM2S Frame delay / Stride register
Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x58, Width*4);
// MM2S HSIZE register
Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x54, Width*2);
// MM2S VSIZE register
Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x50, Height/2);


I have doubled the read stride register size and halfed the vsize register.

I have written a field id extracter based on tuser. 

The data is then forwarded to deinterlacer. Here is the configuration of deinterlacer


/* VPSS Configuration*/

// Set the frame buffer address for the VPSS
VprocCfgPtr = XVprocSs_LookupConfig(XPAR_V_PROC_DINT_DINT_DEVICE_ID);
XVprocSs_CfgInitialize(&VprocInst, VprocCfgPtr, VprocCfgPtr->BaseAddress);

//Get the resolution details
resId = XVidC_GetVideoModeId(Width, Height, XVIDC_FR_60HZ, 0);
TimingPtr = XVidC_GetTimingInfo(resId);

//Set the input stream
StreamIn.VmId = resId;
StreamIn.Timing = *TimingPtr;
StreamIn.ColorFormatId = colorFmtIn;
StreamIn.ColorDepth = VprocCfgPtr->ColorDepth;
StreamIn.PixPerClk = VprocCfgPtr->PixPerClock;
StreamIn.FrameRate = XVIDC_FR_60HZ;
StreamIn.IsInterlaced = 1;
XVprocSs_SetVidStreamIn(&VprocInst, &StreamIn);

//Set the output stream
StreamOut.VmId = resId;
StreamOut.Timing = *TimingPtr;
StreamOut.ColorFormatId = colorFmtIn;
StreamOut.ColorDepth = VprocCfgPtr->ColorDepth;
StreamOut.PixPerClk = VprocCfgPtr->PixPerClock;
StreamOut.FrameRate = XVIDC_FR_60HZ;
StreamOut.IsInterlaced = 0;
XVprocSs_SetVidStreamOut(&VprocInst, &StreamOut);

Status = XVprocSs_SetSubsystemConfig(&VprocInst);
if(Status!= XST_SUCCESS)
xil_printf("VPSS failed\r\n");
xil_printf("VPSS Started\r\n");


the data is then forwarded to axis2video ip core which expects 16 bit (yCbCr 4:2:2) to forward the native data to hdmi on zc702.

vtc default mode is (1080p) without interlaced support

The problem here is, with the above configurations the axi4s_vidout core is not being locked.

It gets locked only when I change the vdma read channel configurations = write_channel configuration

and change the vpss(Deinterlacer)  configurations to StreamIn.IsInterlaced = 0;

I believe either the read side vdma frame buffer start addresses needed to be changed or the vtc configuration needs to be changed. Can you please have your comments on my above configurations. The data flow is
TPG --------->AXI_VDMA(Interlacer)----------->field_id_extracter--------->VPSS(Deinterlacer)------------>VTC+AXIS_Videoout

Here is the block design of the project

After Looking into status signals of axis_vidout, i see that the underflow flag gets high, which means the input stream is slow as compared to timing signals from vtc. For further investigation I removed the vpss(Deinterlacer) from block design and connect the stream output of vdma via fid_extracter to axi4s_vidout_block and parallely changed the constant configuration of VTC from 1080p to 1080i with same VDMA configurations as above. As a result there is no overflow or underflow in axi4s_vidout ip core and it gets locked.

This shows that the deinterlacer configurations are not right.

What do i need to change here to deinterlace the data that is already interlaced with VDMA?

Note: The axi4s_vidout IP block is working properly (getting locked and active_video bit is high) if I generate an interlaced video via tpg instead of vdma and use vproc as deinterlacer with above same configurations.

I will be looking forward to your comments

Best regards,

0 Kudos
3 Replies
Registered: ‎11-18-2012

As VDMA only transfers the image in the vertical direction 1/2, the setting seems to be no problem.

It seems that the missing fid is covered by user logic.


Is it possible to check the input of deinterlacer with ILA and compare it with the case of tpg to see the difference?

Registered: ‎11-21-2018

Hi @abdullah.tukl 


Did this solve your issue? If so, can you mark it as an accepted solution. If not, can you provide the community with an update? 

Product Application Engineer - Xilinx Technical Support EMEA

**~ Got a minute? Answer our Vitis HLS survey here! ~**

**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Registered: ‎11-29-2018

Hi @y_takasugi 

This is a good idea I will hang a debug at tpg Interlaced output and compare it with interlaced output from vdma and provide you with the update by end of this week.

@aoifem Sorry for reacting late as I was interrupted in this project with other issues in an other project. I will post my above mentioned comparisons and will also upload the vivado project to have it reviewed.

Meanwhile if any community member has already tried deinterlacing the already vdma interlaced data with Vpss, It will be helpful to see the results.