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Voyager
Voyager
1,615 Views
Registered: ‎03-17-2011

axis broadcaster

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Hello,

 

I’m updating the UHDSDI passthru example. I need to send the incoming video stream to a Tx SMPTE and at the same time to the frambuffer Wr.

Therefore I've inserted the axis broadcaster. But that does work. I have no video on the Tx SMPTE.

It is expected if you read the documentation: "The Video Broadcaster core performs handshake management and ensures that all the outbound interfaces have completed their TREADY/TVALID handshakes before completing the inbound"

 

However, I need the Tx link active even if the frambuffer Wr is not running.

Any suggestion?

 

Thanks.

 

Sébastien.

--Sebastien
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Moderator
Moderator
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Registered: ‎11-09-2015

Hello @sebo,

 

The only way I see is to create a custom logic on the path of the frame buffer (before the frame buffer):

If you disable the frame buffer, you enable the custom logic to keep to ready high (can be a AXI GPIO IP with a OR on the TREADY signal).

The difficulty here is that you have to manage the synchronization to start writing on the frame buffer on a begining on a frame but it shouldn't be too complicated (kind of trigger on tuser).

 

Regards,

 

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
Moderator
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Registered: ‎11-09-2015

Hello @sebo,

 

The only way I see is to create a custom logic on the path of the frame buffer (before the frame buffer):

If you disable the frame buffer, you enable the custom logic to keep to ready high (can be a AXI GPIO IP with a OR on the TREADY signal).

The difficulty here is that you have to manage the synchronization to start writing on the frame buffer on a begining on a frame but it shouldn't be too complicated (kind of trigger on tuser).

 

Regards,

 

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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Moderator
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1,531 Views
Registered: ‎11-09-2015

Hi @sebo,

 

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" buton below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Voyager
Voyager
1,510 Views
Registered: ‎03-17-2011

Hello Florent,

 

I need to give a try to your suggestion. So far, I haven't been able to find some time.

I'll update the post with the results afterward.

 

Regards

 

S

--Sebastien
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Contributor
Contributor
801 Views
Registered: ‎01-09-2018

Hi Florent. I had a similar question about the b'caster. From your response to the OP, it seems that ready has to be asserted on both masters of the b'caster before it can pass data to either, correct? Now consider a case where one the the sinks of the b'caster is an axi stream switch slave input, but the switch isn't selecting the stream from the b'caster. In this case does the switch send a ready back to the b'caster so that it will not affect thruput on the b'caster's other masters?

Regards, Brian

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Moderator
Moderator
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Registered: ‎11-09-2015

Hi @bmoore ,

I haven't used the AXI4-Stream switch to really be sure but I would not expect it to consume (assert tready) a stream if not using it.

So you probably need to create your own glue logic for this.

If you have following questions, could you kindly create a new topic as this diverge from the original one.

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Contributor
Contributor
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Registered: ‎01-09-2018

Florent, you suggest the following:

"The difficulty here is that you have to manage the synchronization to start writing on the frame buffer on a begining on a frame but it shouldn't be too complicated (kind of trigger on tuser)."

But doesn't the VDMA IP already offer the option of triggering a write into it using TUSER with its fsync options in the GUI? Then the "difficulty" you mention goes away, doesn't it?  If that option is used, then you could force the TREADY high as you suggest?

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Moderator
Moderator
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Registered: ‎11-09-2015

HI @bmoore 

But doesn't the VDMA IP already offer the option of triggering a write into it using TUSER with its fsync options in the GUI? Then the "difficulty" you mention goes away, doesn't it? If that option is used, then you could force the TREADY high as you suggest?

> Yes you are right, this might work. But you still need you own logic to drive TREADY high without transmitting TVALID to the VDMA


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
Moderator
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Registered: ‎11-21-2018

Hi @sebo 

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

 

If this is not solved/answered, please reply in the topic giving more information on your current status.

 

Thanks and Regards,

Aoife
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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