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Visitor
Visitor
1,622 Views
Registered: ‎04-06-2018

axis4-stream problem

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Hello every body
it's my first time to poste something here...
I have a problem in my block design that is acquiring data from a FLIR (HDMI) camera and then sending it back to a VGA monitor.
In the following example, it work when I implement it on FPGA ZYBO board, but I want to convert the frame data to AXis-stream data (to be the input of an HLS IP) but after the implementatio it doen't work, the bistream is generated but I get a black screen
I respected the resolution and the timing but I don't now why it doen't work?
Please help

Capture_fli_t1.PNG

This is my design with the axis4-stream
Capturemmmmmmmmmmmmmmmmmmmm.PNG
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Moderator
Moderator
1,873 Views
Registered: ‎11-09-2015

Hi @azerty,

 

Do you have any updates on this?

 

If everything is clear for you, please kindly close the topic by marking a reply as accepted solution.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

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Moderator
Moderator
1,580 Views
Registered: ‎11-09-2015

Hi @azerty,

 

Your topic is in SDSoC, are you using SDSoC for your design? It might be better in the video board.

 

Then, did you use any ILA on the AXI4S interface?

 

I would check the overflow and underflow outputs from the Video In to AXI4S and AXI4S to Video Out.

 

I would also connect all the clken unconnected to one.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Visitor
Visitor
1,532 Views
Registered: ‎04-06-2018

Hi, thank you for your reply

I'm not using SDSoc for my design, I'm  just using Vivado HLS and Vivado DesignSuit, I can't use any more tool (this is my project and I want to use only Vivado). Also I'm not using any ILA (just axis_stream interfaces)

 

I think that the probleme is some additionals pixels because when I use the design without the axis4_stream, I get my image and some black pixels beside.

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Moderator
Moderator
1,527 Views
Registered: ‎11-09-2015

Hi @azerty,

 

Yes, the AXI4S to video out will need the input data to correspond to the timing. So if it does not match, you won't have any outputs


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Moderator
Moderator
1,874 Views
Registered: ‎11-09-2015

Hi @azerty,

 

Do you have any updates on this?

 

If everything is clear for you, please kindly close the topic by marking a reply as accepted solution.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post