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donghoang22017
Observer
Observer
845 Views
Registered: ‎05-02-2019

bandwidth of xlnxscale plugin

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Hi,

I am using ZCU104 board. In the design in FPGA I use VideoFrameBufferRead, VideoFrameBufferWrite and VideoProcessingSubSystem ip cores to convert YUV format to BGR. Those IP are controlled by gstreamer plugin xlnxscale.

The problems is when the output of xlnxscale is large (for example: input frame is 1920x1080 YUV, output frame is also 1920x1080 BGR), the fps is quite low (about 20fps). 

Can someone provide me the bandwidth of VideoProcessingSubSystem or xlnxscale plugin ???

Thanks in advances !!!

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florentw
Moderator
Moderator
677 Views
Registered: ‎11-09-2015

Hi @donghoang22017 

Can you add a second VPSS configured as color space convertor to do the color space conversion?

So basically change your pipe from

Video Frame Buffer Read (YUV) -> Video Processing Subsystem (Scaler) ->  Video Frame Buffer Write (BGR8)

to

Video Frame Buffer Read (YUV) -> Video Processing Subsystem (CSC) -> Video Processing Subsystem (Scaler) ->  Video Frame Buffer Write (BGR8)

This is how it is done in our examples as the VCU TRD. Else it might be that the conversion is handled by the OS.

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

7 Replies
watari
Professor
Professor
803 Views
Registered: ‎06-16-2013

Hi @donghoang22017 

 

Would you share your gstreamer pipeple ?

 

Best regards,

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donghoang22017
Observer
Observer
788 Views
Registered: ‎05-02-2019

"WIDTH=1920
HEIGHT=1080

WOFF=0
HOFF=0

gst-launch-1.0 filesrc location=video/CIST.mp4 ! qtdemux name=demux demux.video_0 ! h264parse ! omxh264dec internal-entropy-buffers=3 ! xlnxscale need-tdm=true ! \
video/x-raw, width=$WIDTH, height=$HEIGHT, format=BGR ! \
fpsdisplaysink video-sink="kmssink plane-id=29 bus-id="a0070000.v_mix" render-rectangle=\"<$WOFF,$HOFF,$WIDTH,$HEIGHT>\"" text-overlay=true sync=false "

Here is my gstreamer pipeline.

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watari
Professor
Professor
738 Views
Registered: ‎06-16-2013

Hi @donghoang22017 

 

Would you share your clock setting on xlnxscale IP ?

It seems clock frequency issue.

 

Best regards,

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donghoang22017
Observer
Observer
718 Views
Registered: ‎05-02-2019
Hi @watari
In Block Design of FPGA, my xlnxscale IP is using 330MHz clock. I am using the following IPs: Video Frame Buffer Read (YUV), Video Processing Subsystem (Scaler), Video Frame Buffer Write (BGR8).
Best Regards,
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watari
Professor
Professor
716 Views
Registered: ‎06-16-2013

Hi @donghoang22017 

 

How about bus width ?

In this case, you need to consider overhead by CPU.

 

Best regards,

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florentw
Moderator
Moderator
678 Views
Registered: ‎11-09-2015

Hi @donghoang22017 

Can you add a second VPSS configured as color space convertor to do the color space conversion?

So basically change your pipe from

Video Frame Buffer Read (YUV) -> Video Processing Subsystem (Scaler) ->  Video Frame Buffer Write (BGR8)

to

Video Frame Buffer Read (YUV) -> Video Processing Subsystem (CSC) -> Video Processing Subsystem (Scaler) ->  Video Frame Buffer Write (BGR8)

This is how it is done in our examples as the VCU TRD. Else it might be that the conversion is handled by the OS.

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

donghoang22017
Observer
Observer
641 Views
Registered: ‎05-02-2019
Hi florentw,
I tried as your suggestions and it improved the performance. Thanks in advances ! :D
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