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Adventurer
Adventurer
1,570 Views
Registered: ‎02-04-2017

can XC7K325T use hdmi 2.0 ip in MGT116?

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we use hdmi2.0 ip on the MGT116 of xc7k325T, but we find that HDMI on xc7k325T cann't change MGT pin.

捕获.PNG

 

can XC7K325T use hdmi 2.0 ip  in MGT116? if it can, how to change pin form MGT118 to MGT116?

 

 

 

 

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Moderator
Moderator
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Registered: ‎11-09-2015

HI @autelchengpeng,

 

Are you still using the same clock as in the example design or did you change his pin as well?

 

You need to follow the correct ruler for the GTs and assign the clock properly. If the clock is coming from the same quad as you GT you can use the basic MGTCLK port . If it is coming from an adjacent quad (south or north), you need to use the advanced clocking mode in the video phy. Also this imply that your clock needs to be coming from the GT quad or from an adjacent quad.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

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Xilinx Employee
Xilinx Employee
1,540 Views
Registered: ‎03-30-2016

Hello @autelchengpeng

 

Your Video PHY controller pin assignment is controlled by XDC file.

Please find the following lines on your FPGA design constrain file (XDC), then modify the pin assignment accordingly.

 

set_property PACKAGE_PIN ** [get_ports {HDMI_TX_DAT_P_OUT[?]}]
set_property PACKAGE_PIN ** [get_ports {HDMI_RX_DAT_P_IN[?]}]

 

Thanks & regards

Leo

Adventurer
Adventurer
1,531 Views
Registered: ‎02-04-2017

hello,

     i change pin xdc to mgt116, for below show,  more information see attchment file.

 

# HDMI RX
#FMC_HPC_GBTCLK0_M2C_C_P
set_property PACKAGE_PIN N8 [get_ports HDMI_RX_CLK_P_IN]
#SGMIICLK_Q0_P #PCIE_CLK_QO_P
set_property PACKAGE_PIN R8 [get_ports DRU_CLK_IN_clk_p]
#FMC_HPC_DP0_M2C_P
set_property PACKAGE_PIN T6 [get_ports {HDMI_RX_DAT_P_IN[0]}]
#FMC_HPC_DP1_M2C_P
set_property PACKAGE_PIN R4 [get_ports {HDMI_RX_DAT_P_IN[1]}]
#FMC_HPC_DP2_M2C_P
set_property PACKAGE_PIN P6 [get_ports {HDMI_RX_DAT_P_IN[2]}]

 

but vivado2016.4 error create,  it change pin fail.

23%LUE0AWX%QN1VL(F~YULR.png

 

i think XC7K325T cann't change hdmi pin to mgt116, we must use example's mgt118. isn't it?

 

 

 

 

 

 

 

 

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Adventurer
Adventurer
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Registered: ‎02-04-2017

hello,

   it is my xdc file.
#####
## Constraints for KC705 FMC HDMI 2.0
## Version 1.0
#####

#####
## Clocks
#####
#create_clock -period 3.367 -name mgtclk0 [get_ports HDMI_RX_CLK_P_IN]
#create_clock -period 3.367 -name mgtclk1 [get_ports TX_REFCLK_P_IN]
#create_clock -period 8.000 -name druclk [get_ports DRU_CLK_IN_clk_p]


#####
## Pins
#####

# HDMI RX
#FMC_HPC_GBTCLK0_M2C_C_P
set_property PACKAGE_PIN N8 [get_ports HDMI_RX_CLK_P_IN]
#SGMIICLK_Q0_P #PCIE_CLK_QO_P
set_property PACKAGE_PIN R8 [get_ports DRU_CLK_IN_clk_p]
#FMC_HPC_DP0_M2C_P
set_property PACKAGE_PIN T6 [get_ports {HDMI_RX_DAT_P_IN[0]}]
#FMC_HPC_DP1_M2C_P
set_property PACKAGE_PIN R4 [get_ports {HDMI_RX_DAT_P_IN[1]}]
#FMC_HPC_DP2_M2C_P
set_property PACKAGE_PIN P6 [get_ports {HDMI_RX_DAT_P_IN[2]}]

#FMC_HPC_LA20_N
set_property PACKAGE_PIN E16 [get_ports RX_HPD_OUT]
set_property IOSTANDARD LVCMOS25 [get_ports RX_HPD_OUT]

set_property IOSTANDARD LVCMOS25 [get_ports rx_ddc_out_scl_io]
set_property IOSTANDARD LVCMOS25 [get_ports rx_ddc_out_sda_io]
#FMC_HPC_LA16_P
set_property PACKAGE_PIN F15 [get_ports rx_ddc_out_scl_io]
#FMC_HPC_LA16_N
set_property PACKAGE_PIN E14 [get_ports rx_ddc_out_sda_io]

set_property IOSTANDARD LVDS_25 [get_ports RX_REFCLK_P_OUT]
#FMC_HPC_LA00_CC_P
set_property PACKAGE_PIN E28 [get_ports RX_REFCLK_P_OUT]

set_property IOSTANDARD LVCMOS25 [get_ports RX_DET_IN]
#FMC_HPC_LA03_P
set_property PACKAGE_PIN E15 [get_ports RX_DET_IN]


# HDMI TX
#FMC_HPC_GBTCLK1_M2C_C_P
set_property PACKAGE_PIN L8 [get_ports TX_REFCLK_P_IN]

set_property IOSTANDARD LVDS_25 [get_ports HDMI_TX_CLK_P_OUT]
#FMC_HPC_LA27_P
set_property PACKAGE_PIN C25 [get_ports HDMI_TX_CLK_P_OUT]

set_property IOSTANDARD LVCMOS25 [get_ports TX_HPD_IN]
#FMC_HPC_LA31_N
set_property PACKAGE_PIN D11 [get_ports TX_HPD_IN]

set_property IOSTANDARD LVCMOS25 [get_ports tx_ddc_out_scl_io]
set_property IOSTANDARD LVCMOS25 [get_ports tx_ddc_out_sda_io]
#FMC_HPC_LA29_P
set_property PACKAGE_PIN C12 [get_ports tx_ddc_out_scl_io]
#FMC_HPC_LA29_N
set_property PACKAGE_PIN B12 [get_ports tx_ddc_out_sda_io]


## UART
set_property IOSTANDARD LVCMOS25 [get_ports rs232_uart_rxd]
##USB_TX
set_property PACKAGE_PIN W22 [get_ports rs232_uart_rxd]
set_property IOSTANDARD LVCMOS25 [get_ports rs232_uart_txd]
##USB_RX
set_property PACKAGE_PIN W21 [get_ports rs232_uart_txd]


# I2C
set_property IOSTANDARD LVCMOS25 [get_ports fmch_iic_scl_io]
#FMC_HPC_LA06_P
set_property PACKAGE_PIN E11 [get_ports fmch_iic_scl_io]
set_property IOSTANDARD LVCMOS25 [get_ports fmch_iic_sda_io]
#FMC_HPC_LA06_N
set_property PACKAGE_PIN A11 [get_ports fmch_iic_sda_io]


set_property IOSTANDARD LVCMOS25 [get_ports SI5324_RST_OUT]
#FMC_HPC_LA10_P
set_property PACKAGE_PIN D23 [get_ports SI5324_RST_OUT]

set_property IOSTANDARD LVCMOS25 [get_ports SI5324_LOL_IN]
#FMC_HPC_LA02_N
set_property PACKAGE_PIN E23 [get_ports SI5324_LOL_IN]

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Xilinx Employee
Xilinx Employee
1,516 Views
Registered: ‎03-30-2016

Hello  @autelchengpeng

 

What is the device package you are using ?
I do not know the device model you are  using. ( I am assuing XC7K325T-FFV900 )
-- It would be better if you can share your Exact device model/Vivado version/XCI file
   so Forum Moderator can give you an accurate advice.

I looked at the screenshots you have uploaded.
1. You are using QPLL for both TX and RX. Do you have a special reason using this setting ?
    I believe this  is not allowed. Please see PG230 Chapter 3.
2. I cannot see the pin assignment of your HDMI TX pins.
    Do you assign all of the following pins correctly ?

   set_property PACKAGE_PIN ** [get_ports {HDMI_TX_DAT_P_OUT[*]}]
   set_property PACKAGE_PIN ** [get_ports {HDMI_TX_DAT_P_OUT[*]}]
   set_property PACKAGE_PIN ** [get_ports {HDMI_TX_DAT_P_OUT[*]}]
   
Thanks & regards
Leo

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Adventurer
Adventurer
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Registered: ‎02-04-2017

because of base on  the hdmi2.0 example of kc705, i only change the pin in xdc,  in the example of hdmi, only fixed RX pin. 

so i am also use  XC7K325T-FFV900 , and  use  CPLL for TX and QPLL for RX, and change rx's pin in the xdc. 

 

AZ1}VL{3GQL1L$R%TN]GF6T.jpg

 

i can't change MGT bank, but if i use fpga's xkcu040, i can change Bank. so i think XC7K325T's hdmi only use MGT118.

]2Z2U~MQ@XE}DRCAU]9)88U.jpg

 

 

 

  

 

 

 

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Xilinx Employee
Xilinx Employee
1,502 Views
Registered: ‎03-30-2016

Hello @autelchengpeng

1. I am not sure if I can understand you correctly.
   Please let me check my understanding.
   
 You are creating a FPGA design based on HDMI Example Design targeting KC705.
 You keep the HDMI TX pin assignment as is ( on MGT118).
 but you only changed RX pin assignment to MG116.
    
  Is my understanding above correct ? (Then it might not worked)

2. Xilinx IP wizard has a slightly different behavior when targeting different device.
   When you are targeting 7-series. You cannot set the GT location from IP GUI.
   This is expected behavior. So corresponding pin assignment constraint must be added in the top-level XDC for designs targeting 7-series

    
Thanks & regards
Leo

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Adventurer
Adventurer
1,492 Views
Registered: ‎02-04-2017

Hello karnanl

    Yes, what you understand is right, but i add TX pin assignment to MG116, it is the same error。

 

捕获.PNG

 

the error picture is below:

捕获1.PNG

 

so it is not error of TX pin assignment to MG116, i think maybe the hdmi ip in the xc7k325t have specail problem.

 

 

 

 

    

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Moderator
Moderator
1,486 Views
Registered: ‎11-09-2015

HI @autelchengpeng,

 

Are you still using the same clock as in the example design or did you change his pin as well?

 

You need to follow the correct ruler for the GTs and assign the clock properly. If the clock is coming from the same quad as you GT you can use the basic MGTCLK port . If it is coming from an adjacent quad (south or north), you need to use the advanced clocking mode in the video phy. Also this imply that your clock needs to be coming from the GT quad or from an adjacent quad.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

Moderator
Moderator
1,406 Views
Registered: ‎11-09-2015

Hello @autelchengpeng,

 

Do you have any updates on this? Did on of the replies helped you?

If your question is answered or your issue is solved, please mark the response which helped as solution (click on the button "Accept as solution" below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Best Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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