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Registered: ‎08-15-2017

can axi vdma be used to transfer ordinary data except video frame data ?

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I am using axi vdma,and I make a data_source IP,which can generate 32linex32row frame pixels(16bits width,and it is not real video frame data,but composed by analogy data from xadc and other datas ) ,and I using axi vdma transfer the data from the data_source IP to DDR, the clock of stream and writing DDR are all 200mhz,and the system is OK.

but I want to transfer a stream which  is drived by a 1mhz clock to DDR via the axi vdma ,can I do that ?

I try like below:

1) using a 5mhz(it seem that 5mhz is the lowest clock frequency coming out from the MMCM  or PLL,and just using it replaced the 1mhz clock) clock from  MMCM to drive the data_source IP, and the clock writing the DDR is 200mhz,

that is the clock frequency of the S_AXIS_S2MM bus is 5mhz, but the clock frequency of the  M_AXI_S2MM is 200mhz,and can the  axi vdma   work ?

2) using a the 200mhz to drive data_source IP and the clock writing the DDR ,but add gap between the frame of the data_source IP,the time gap is  10ms using a counter, the result is that the axi VDMA  halt ,can I use axi vdma like that ?

 

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Registered: ‎11-09-2015

HI @microchip_zhang 


@microchip_zhang wrote:

1) I am keep on working on vdma, and build a system shown below, and the status of s2mm is 0x00015100, and please pay attention to the wave of the tready, when a new frame begin , the tuser is pull on ,and just one clock the tready switch to low,why?

I do not know but this could be related to multiple things: for example it an be linked to the error you are getting. Or it could be because there is BW issues with the memory. I suggest you fix the EOL error first


2) I set 32rowx32colum in TPG, and is it just 2bytes for one pixel of the TPG,right ?

Yes for the pixel itself. However the AXI VDMA is not aware that the full interface is not used. So what he sees is a 32-bit interface. So each pixel are 32-bit, ie 3byte


3) there are EOLEarlyErr ,what's wrong with my setting ?
for I  want to transfer ordinary data(is not the video frame) using the vdma ,so I set the dimensions of the frame si 32x32 for TPG 


I do not know. My first recommendation would be to use a newer version to make sure this is not an issue with the IPs in the version you are using.

And again, the AXI VDMA is not meant to work with so small resolutions. Try with 128*128 (which would be the size of the line buffer) and see if this is still happening


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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HI @microchip_zhang 

The main question is why would you use the AXI Video DMA (VDMA) if you are not planning to transfer video.

The AXI VDMA has a kind of layer on top of the AXI DMA. This is used to take care of the video signals like Start of Frame and End of Frame. If you do not have this signals the AXI VDMA will fail. This might be why you see the failures.

Why not using the AXI DMA instead?


Florent
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HI @microchip_zhang 

Is everything clear for you on this topic? If yes, could you kindly mark the correct reply as accepted solution to close the thread?

Thanks and Regards


Florent
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Registered: ‎08-15-2017

Thanks for your reply,
I have read the document of the dma and the axi vdma,
first of all , it is just single direction for my function, I just want to PL to write the data to ddr buffer and PS will read the data from the ddr buffer, the source data is drived by a 1m clock,and the data will be generated continually without stop
Using the axi VDMA, if I set "Frame Buffers" is 2 , it seem that AXI VDMA will implement the pingpang operation automaticly, after setting the two ddr buffer address of the AXI VDMA, then the VDMA will write one ddr buffer ,when completed an interrput will be generated, and then VDMA will write another buffer automaticly ,then another interrupt will be generated . And the pingpang operation will be cycled automaticly.
but if I use AXI DMA to implement the function ,it seem complex, that the satter-gather mode of the AXI DMA must be used to implement the pingpang operation,right? and I must create a link table giving the next address of the ddr buffer, if I just have two ddr buffer,the link table for this structure must be created and menaged too, right ?

the above is the reason why I want to use AXI VDMA to transfer ordinary data except video frame data instead of AXI DMA.

if I must use AXI DMA to implement the function, the Satter-Gather mode of the axi DMA must be used ,right?
and can Direct Register Mode of AXI DMA be used to implement the pingpang operation?

And will you please give me any advice about the usage of axi dma to implement the pingpang operaton to transfer data from stream to ddr, and then ps will read the data from the ddr,and the data source is drived with 1M clock ,and the data will be generated will be generated continually without any interrupt ?

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Registered: ‎11-09-2015

HI @microchip_zhang 

I have read the document of the dma and the axi vdma,
first of all , it is just single direction for my function, I just want to PL to write the data to ddr buffer and PS will read the data from the ddr buffer, the source data is drived by a 1m clock,and the data will be generated continually without stop
Using the axi VDMA, if I set "Frame Buffers" is 2 , it seem that AXI VDMA will implement the pingpang operation automaticly, after setting the two ddr buffer address of the AXI VDMA, then the VDMA will write one ddr buffer ,when completed an interrput will be generated, and then VDMA will write another buffer automaticly ,then another interrupt will be generated . And the pingpang operation will be cycled automaticly.

Yes but if you data does not fake the signals for video, then the AXI VDMA will always stop with errors


but if I use AXI DMA to implement the function ,it seem complex, that the satter-gather mode of the AXI DMA must be used to implement the pingpang operation,right? and I must create a link table giving the next address of the ddr buffer, if I just have two ddr buffer,the link table for this structure must be created and managed too, right ?

Well. Yes I believe you need to have the scatter gather enabled but it can be only 2 descriptor and you are cycling through them. So once it is running, you do not need PS intervention.

And will you please give me any advice about the usage of axi dma to implement the pingpang operaton to transfer data from stream to ddr, and then ps will read the data from the ddr,and the data source is drived with 1M clock ,and the data will be generated will be generated continually without any interrupt ?


To be honest I think this is easier if you use a PS with interrupts. This would give you more control


Florent
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Thank for your reply,I have read your reply carefully,

And now I have created a project shown in the figure 1, and the "src_data5_0" will generate data drived by 1m clk, and the s_axis_aclk of the "axis_data_fifo_0" is 1m clock, and the m_axis_aclk of the "axis_data_fifo_0" is 200m clock;

The pattern of the the "src_data5_0" is 32rowx32column fake frame video data, every pixel is 16bits, now my project is working, and the interface of "src_data5_0" is shown in figure2,

and the setting of axi_vdma is shown in figure31 and figure32, and the m_axis_video_tuser will be pull up for one clock at the beginning pixel of the fake video frame , I have notice that the tlast do not indicate the end of one burst ,but indicate the end of the row in video pattern , and the "write burst size" of vdma is set to 32, so m_axis_video_tlast will be pull up for one clock to indicate the end of one row of the fake frame(for burst it is right ,too ) , but now the data of the status register is 0x00017100 , the error is EOLEarlyErr shown in figure4,can the 32linex32row data block,the fake frame (every pixel has 16bits) be treated as a video frame ? where is wrong?

figure1.pngfigure2.pngfigure31.pngfigure32.pngfigure4.png

 

 

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Registered: ‎08-15-2017

the figure  can not be inserted in the fomer ,and inserted here

figure5.pngfigure6.png

so the reason of the status register error  is for the fake frame can not be treated as video frame, or any setting  is not right ?

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HI @microchip_zhang 

Make sure you read the following articles about configuring and debugging the AXI VDMA:

Video Series 24: Using the AXI VDMA in Triple Buffer Mode

Video Series 25: Debugging issues on the AXI VDMA IP

The first will help you to check if your configuration is correct.

The second will point out that there might be some errors flagged while starting the AXI VDMA but you need to clear them to see if they are consistent.

Then the only way we could comment on a EOLEarlyErr would be by looking at the waveform to see if you have inserted the tlast as expected


Florent
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thank you,

I have read the two articles and check my setting,

and now I  use  the TPG to  replace the position of  the self-defined ip src_data5,and TPG is connected to "axis_data_fifo_0",and the TPG is drived by 1m clock,I think the siginal (including tuser and tlast )of the TPG is right of course, and the status register is still  0x00017100 , and 

can a video frame of  1m clock  be transfer to a axi_vdma driver by 200m clock , via a  "axis_data_fifo_0" ? Whether the  structure of the project is right or not ?

the setting of the TPG  is shown below:

 

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ddd1.png

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HI @microchip_zhang 

Yes this is possible. This is probably a mistake in your configuration.

Keep in mind that you have to program HSIZE in number of bytes knowing that you have to count the bytes which are not used.

So if you connected the TPG directly to the AXI VDMA assuming this is 8-bits 1 ppc, this would be width * 3 (as the TPG output will be 24-bits).

My example is using the AXI VDMA and the TPG. I suggest you try with it as this is working

 


Florent
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for XVES_0026, the error is shown below, can you provide me a whole example

BBB2.png

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HI @microchip_zhang 

Refer to the steps in the article. You need to use the tcl files which are in the example folder

  1. Open Vivado 2018.1

  2. In the Tcl console, cd into the unzipped directory (cd example_x/hw)

  3. In the Tcl console, source the script tcl (source ./create_proj.tcl)

Florent
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1) I am keep on working on vdma, and build a system shown below, and the status of s2mm is 0x00015100, and please pay attention to the wave of the tready, when a new frame begin , the tuser is pull on ,and just one clock the tready switch to low,why?
2) I set 32rowx32colum in TPG, and is it just 2bytes for one pixel of the TPG,right ?
3) there are EOLEarlyErr ,what's wrong with my setting ?
for I  want to transfer ordinary data(is not the video frame) using the vdma ,so I set the dimensions of the frame si 32x32 for TPG 

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a2.pnga3.pngb1.pngb2.pngb3.png

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HI @microchip_zhang 


@microchip_zhang wrote:

1) I am keep on working on vdma, and build a system shown below, and the status of s2mm is 0x00015100, and please pay attention to the wave of the tready, when a new frame begin , the tuser is pull on ,and just one clock the tready switch to low,why?

I do not know but this could be related to multiple things: for example it an be linked to the error you are getting. Or it could be because there is BW issues with the memory. I suggest you fix the EOL error first


2) I set 32rowx32colum in TPG, and is it just 2bytes for one pixel of the TPG,right ?

Yes for the pixel itself. However the AXI VDMA is not aware that the full interface is not used. So what he sees is a 32-bit interface. So each pixel are 32-bit, ie 3byte


3) there are EOLEarlyErr ,what's wrong with my setting ?
for I  want to transfer ordinary data(is not the video frame) using the vdma ,so I set the dimensions of the frame si 32x32 for TPG 


I do not know. My first recommendation would be to use a newer version to make sure this is not an issue with the IPs in the version you are using.

And again, the AXI VDMA is not meant to work with so small resolutions. Try with 128*128 (which would be the size of the line buffer) and see if this is still happening


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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